IP core for signal clipping for Xilinx FPGA

osbourne said:

I need an IP core for signal clipping for Xilinx FPGA.
Does anybody know wether such a core exists ?

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PARAMETERS (LEVEL =175);
...
SIGNAL up_level :NODE;
...
up_level = (data_in >= LEVEL);
CASE up_level IS
WHEN '0' =>
data_out = data_in;
WHEN OTHERS =>
data_out = LEVEL;
END CASE;
...

osbourne said:

I need an ip core which implements a soft clipping algorithm to reduce the peak to average ratio of communications signals (e.g. in umts). Simply cutting a signal above some level is called hard clipping, but this results in strong intermodulation products.
By using soft clipping, intermodulation can be kept to a minimum while reducing the peak to average ratio of the signal.

Can somebody help ?

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osbourne said:

I think A-law and u-law are similar to the clipping characteristic of a power amplifier, but this is not good enough. I need a special algorithm called windowing, implemented as ip core.

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