[SOLVED] getting 'No such file or directory' message, but files are there

kvn0smnsn · Nov 21, 2022

I've got four different modules that I'm using in an attempt to divide a six-bit value by ten, and then calculate a quotient and a remainder.
If I put them all in one file, it works just fine.
But if I put them in four different files like so:

Mux.v:

Code:

module Mux #( nmBits = 1)
           ( result, control, hgVal, lwVal);
  output [ nmBits-1:0] result;
  input                control;
  input  [ nmBits-1:0] hgVal;
  input  [ nmBits-1:0] lwVal;

  genvar bt;
  generate
    for (bt = 0; bt < nmBits; bt = bt + 1)
    begin
      assign result[ bt] = control ? hgVal[ bt] : lwVal[ bt];
    end
  endgenerate

endmodule

and FullAdder.v:

Code:

module FullAdder( cOut, sum, aOp, bOp, cIn);
  output cOut;
  output sum;
  input  aOp;
  input  bOp;
  input  cIn;

  assign cOut = aOp & bOp | aOp & cIn | bOp & cIn;
  assign sum  = aOp ^ bOp ^ cIn;
endmodule

and AddVector.v:

Code:

`include "C:\\Users\\Kevin\\Uvu\\3740\\Ds\\Final\\Params\\Inc\\FullAdder.v"

module AddVector #( nmBits = 1)
                 ( sum, aOp, bOp);
  output [ nmBits  :0] sum;
  input  [ nmBits-1:0] aOp;
  input  [ nmBits-1:0] bOp;
  wire   [ nmBits  :0] carry;

  assign carry[ 0]    = 1'b0;
  assign sum[ nmBits] = carry[ nmBits];

  genvar bt;
  generate
    for (bt = 0; bt < nmBits; bt = bt + 1)
    begin
      FullAdder fa( carry[ bt + 1], sum[ bt], aOp[ bt], bOp[ bt], carry[ bt]);
    end
  endgenerate

endmodule

and then finally DivByTen.v:

Code:

`include "C:\\Users\\Kevin\\Uvu\\3740\\Ds\\Final\\Params\\Inc\\AddVector.v"
`include "C:\\Users\\Kevin\\Uvu\\3740\\Ds\\Final\\Params\\Inc\\Mux.v"

module DivByTen( quotient, remainder, dividend);
  output [ 2:0] quotient;
  output [ 3:0] remainder;
  input  [ 5:0] dividend;
  wire   [ 6:0] sum40;
  wire   [ 6:0] sum20;
  wire   [ 5:0] sum10;
  wire   [ 5:0] result40;
  wire   [ 4:0] result20;
  wire   [ 3:0] result10;

  AddVector av40 #(6)( sum40, dividend, 6'b011000);   // Subtract 40.
  AddVector av20 #(6)( sum20, result40, 6'b101100);   // Subtract 20.
  AddVector av10 #(5)( sum10, result20, 5'b10110 );   // Subtract 10.

  // For each mux, pass through the least significant bits of the sum if the
  // most significant bit is high, which indicates the subtraction is positive;
  // otherwise pass through the value before the subtraction.
  Mux mx40 #(6)( result40, sum40[ 6], sum40[ 5:0], dividend);
  Mux mx20 #(5)( result20, sum20[ 6], sum20[ 4:0], result40[ 4:0]);
  Mux mx10 #(4)( result10, sum10[ 5], sum10[ 3:0], result20[ 3:0]);

  assign quotient[ 2] = sum40[ 6];
  assign quotient[ 1] = sum20[ 6];
  assign quotient[ 0] = sum10[ 5];
  assign remainder    = result10;

endmodule

and then I bring "DivByTen.v" into EDA Playground and click on <Run>, I get
message:

Parsing design file 'design.sv'

Error-[SFCOR] Source file cannot be opened
Source file "C:\Users\Kevin\Uvu\3740\Ds\Final\Params\Inc\AddVector.v" cannot
be opened for reading due to 'No such file or directory'.
Please fix above issue and compile again.
"design.sv", 1
Source info: `include
"C:\\Users\\Kevin\\Uvu\\3740\\Ds\\Final\\Params\\Inc\\AddVector.v"

1 error
CPU time: .140 seconds to compile
Exit code expected: 0, received: 1
Done

Note that if I execute the following command I get these results:

C:\Users\Kevin\Uvu\3740>dir C:\Users\Kevin\Uvu\3740\Ds\Final\Params\Inc
Volume in drive C has no label.
Volume Serial Number is 843B-37F1

Directory of C:\Users\Kevin\Uvu\3740\Ds\Final\Params\Inc

11/21/2022 08:50 AM <DIR> .
11/21/2022 08:50 AM <DIR> ..
11/21/2022 08:55 AM 540 AddVector.v
11/21/2022 08:56 AM 1,233 DivByTen.v
11/10/2022 08:50 PM 221 FullAdder.v
11/17/2022 09:08 PM 383 Mux.v
11/21/2022 09:03 AM 4,330 NoSuchFile.Txt
11/21/2022 08:42 AM 1,094 t_DivByTen.v
6 File(s) 7,801 bytes
2 Dir(s) 140,274,835,456 bytes free

C:\Users\Kevin\Uvu\3740>

So all the files are actually there. Why is EDA Playground telling me 'No such file or directory'?

flyline19 · Nov 21, 2022

Does your AddVector.v file compile and run fine?

kvn0smnsn · Nov 21, 2022

flyline19 said:
Does your AddVector.v file compile and run fine?

No flyline19, I threw together "t_AddVector.v" like so:

Code:

module t_AddVector;
  reg  [ 2:0] aOpe;
  reg  [ 2:0] bOpe;
  wire [ 3:0] abSum;
  
  initial
  begin
    aOpe    = 3'b001;
    bOpe    = 3'b010;
    #2 aOpe = 3'b011;
    bOpe    = 3'b101;
  end
  
  always @( abSum)
  begin
    $display
      ( "time: %2d, aOpe: %d, bOpe: %d, abSum: %d", $time, aOpe, bOpe, abSum);
  end
  
endmodule

and added it and "AddVector.v" to EDA Playground, and clicked <Run>, and got a similar message to the one when I clicked <Run> for the previous file:

Code:

Parsing design file 'design.sv'

Error-[SFCOR] Source file cannot be opened
  Source file "C:\Users\Kevin\Uvu\3740\Ds\Final\Params\Inc\FullAdder.v" cannot
  be opened for reading due to 'No such file or directory'.
  Please fix above issue and compile again.
  "design.sv", 1
  Source info: `include 
  "C:\\Users\\Kevin\\Uvu\\3740\\Ds\\Final\\Params\\Inc\\FullAdder.v"

1 error
CPU time: .136 seconds to compile
Exit code expected: 0, received: 1
Done

I'm still at a loss as to why it doesn't see "FullAdder.v". It exists in that directory.

kvn0smnsn · Nov 21, 2022

kvn0smnsn said:

No flyline19, I threw together "t_AddVector.v" like so:

Code:

module t_AddVector;
  reg  [ 2:0] aOpe;
  reg  [ 2:0] bOpe;
  wire [ 3:0] abSum;
 
  initial
  begin
    aOpe    = 3'b001;
    bOpe    = 3'b010;
    #2 aOpe = 3'b011;
    bOpe    = 3'b101;
  end
 
  always @( abSum)
  begin
    $display
      ( "time: %2d, aOpe: %d, bOpe: %d, abSum: %d", $time, aOpe, bOpe, abSum);
  end
 
endmodule

and added it and "AddVector.v" to EDA Playground, and clicked <Run>, and got a similar message to the one when I clicked <Run> for the previous file:

Code:

Parsing design file 'design.sv'

Error-[SFCOR] Source file cannot be opened
  Source file "C:\Users\Kevin\Uvu\3740\Ds\Final\Params\Inc\FullAdder.v" cannot
  be opened for reading due to 'No such file or directory'.
  Please fix above issue and compile again.
  "design.sv", 1
  Source info: `include
  "C:\\Users\\Kevin\\Uvu\\3740\\Ds\\Final\\Params\\Inc\\FullAdder.v"

1 error
CPU time: .136 seconds to compile
Exit code expected: 0, received: 1
Done

I'm still at a loss as to why it doesn't see "FullAdder.v". It exists in that directory.

When I said "threw together" I wasn't kidding! Here's a better version of "t_AddVector.v":

Code:

module t_AddVector;
  reg  [ 2:0] aOpe;
  reg  [ 2:0] bOpe;
  wire [ 3:0] abSum;
  
  AddVector #(3) av( abSum, aOp, bOp);

  initial
  begin
    aOpe    = 3'b001;
    bOpe    = 3'b010;
    #2 aOpe = 3'b011;
    bOpe    = 3'b101;
  end
  
  always @( abSum)
  begin
    $display
      ( "time: %2d, aOpe: %d, bOpe: %d, abSum: %d", $time, aOpe, bOpe, abSum);
  end
  
endmodule

I got the same result when I clicked on <Run> though.

flyline19 · Nov 21, 2022

It seems like you just have an issue with reading from your directory in general, not necessarily with your code. I don't know this language but I have had similar issues with python. Are you sure that either eda playground is reading from the correct directory/ is located in the correct directory, and if so, are you sure that the syntax for reading a ".v" file is correct or must include something else?

I'm just shooting in the dark here. Maybe you don't need to include the file extension when calling it from the directory... i doubt it but who knows

FvM · Nov 21, 2022

You are simulating on EDA Playground, not on your computer. EDA Playground can't access files on your computer, all design files have to be uploaded before. EDA Playground uses a single folder with all design files, no subfolders. Respectively an include statement has a simple file argument, no drive or directory info.

kvn0smnsn · Nov 22, 2022

FvM said:
You are simulating on EDA Playground, not on your computer. EDA Playground can't access files on your computer, all design files have to be uploaded before. EDA Playground uses a single folder with all design files, no subfolders. Respectively an include statement has a simple file argument, no drive or directory info.

FvM, how do I upload a file so that I can include it in my module?

dpaul · Nov 22, 2022

@kvn0smnsn
Do you how to use internet search?

I searched with the phrase "EDA playground upload files" and could find the answer within 20 seconds!
It is right there inside the FAQ section.

ads-ee · Nov 22, 2022

Also don't use include files to "include" Verilog HDL files into another file. There is a post in the FPGA section where a member is doing the same thing.

Just compile each HDL source file separately. Verilog isn't like VHDL where it needs library references or component declarations to find everything.

kvn0smnsn · Nov 22, 2022

dpaul said:
@kvn0smnsn
Do you how to use internet search?

I searched with the phrase "EDA playground upload files" and could find the answer within 20 seconds!
It is right there inside the FAQ section.

Thanks Dpaul! I was able to get it working with your and everyone else's comments.

dpaul · Nov 23, 2022

@kvn0smnsn
Good, so if your question is answered, then please mark the thread as Solved.

Welcome to EDAboard.com

[SOLVED] getting 'No such file or directory' message, but files are there

kvn0smnsn

Junior Member level 2

kvn0smnsn

flyline19

Newbie level 5

kvn0smnsn

Junior Member level 2

kvn0smnsn

Junior Member level 2

flyline19

Newbie level 5

kvn0smnsn

FvM

Super Moderator

flyline19

kvn0smnsn

kvn0smnsn

Junior Member level 2

dpaul

Advanced Member level 5

flyline19

kvn0smnsn

ads-ee

Super Moderator

kvn0smnsn

kvn0smnsn

Junior Member level 2

dpaul

Advanced Member level 5

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Connect with us

Online statistics

Forum statistics