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biasing current circuit that change opposite to process corner

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Junus2012

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Hello,

The PTAT beta multiplier current source is serving my purpose for biasing my amplifier. The temperature behavioural of the biasing current is well compensating the variation of the opamp under the change of temperature.

However, with the slow process corner, the opamp bandwidth goes down, and in order to compensate it I need to increase the biasing current. On the other hand, the current of the biasing circuit is minimum at the slow corner, so what I need is a circuit that works opposite to the process corner with regards to the biasing circuit, that is at the slow corner the biasing current becomes maximum and at the fast corner, the current will be minimum. In either cases the current should have PTAT properties.


Thank you in advance for your help
Regards
 

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One issue is that analog has more variation dimensions than a finite set of corner model cases can represent. And a sub-issue is that corner cases like FS and SF are processing-unrealistic to encounter.

You need something to count on, for any compensation scheme. Or accept a residual variation if reference & feedback can't be applied (like a standalone op amp guts).

A 1-2 bit trim could be more production-useful than a set-and-pray comp scheme but then you have to touch every die and develop a method to pick a trim target.

You might consider a simple deal like a biased HVT stack, used as a crude ref for a resistor-fed mirror master. If one device species is especially responsible for key attributes this may be efficient. You could make a "combo comp" by stacking HVT N and P in the ref stack. Choose the resistor for best outcome in P,T space (tempco, make).
 
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Are you using a resistor in your PTAT current source? It is the corner of the resistor that is setting the Current.
Technically, you need an impedance there which, across corners, goes opposite to the MOS corners. And there you will have your solution.
You can try things like using a biased MOS as your resistor and have the bias such that the impedance from the MOSFET across corners is the way you want it.

Usually in corner files provided by the foundry, SS corner means Everything including MOS, RES, CAP, etc is slow. And the same for FF.
But it is also possible that you might have MOS in SS and RES in Fast and hte vice versa as well. Which might result in a large numbers of corner cases to be dealt with.

Trimming the resistor with a few bits might be the easiest solution if you have provision to do it.
 
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Thank you friends for your reply,

I understood now from you that I shouldn't rely on correcting any circuit behavioural based on corners, because real fabrication have many possible corner combination more than the simple FF,SS,FS,SF,TM. on the other hand to think about compensation with respect to MC is tedious.

I conclude that digital trimming is the best option.

Thank you once again
Regards
 

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The task is not impossible. But it is convoluted.

You have a PTAT current source which varies with Res Corners.
If you want it to vary with Mos Corners you need to ensure that the MOS it self does not vary with temperature ( otherwise it wont be PTAT ). For that you would need it to be biased with a separate biasing circuit which might be constant voltage or constant current.
And now that biasing circuit might need to be trimmed.
It will be a reference driving a reference driving a reference....!

For a project, we had come up with a solution where we used one Current Reference which was trimmed. This trimmed current reference and the BGR provided us with a process independent Voltage and Current. This was now used for generating other types of biases as needed. Mainly it was used for a constant Gm bias. The idea was that this way, a single trimming will allow us to get an ideal of resistor corner on the chip and that information is reused elsewhere. This does not consider the mismatch of the devices across the different blocks across the chip. The spec wasn't that tight.
 
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nitishn5 said:
The task is not impossible. But it is convoluted.

You have a PTAT current source which varies with Res Corners.
If you want it to vary with Mos Corners you need to ensure that the MOS it self does not vary with temperature ( otherwise it wont be PTAT ). For that you would need it to be biased with a separate biasing circuit which might be constant voltage or constant current.
And now that biasing circuit might need to be trimmed.
It will be a reference driving a reference driving a reference....!

For a project, we had come up with a solution where we used one Current Reference which was trimmed. This trimmed current reference and the BGR provided us with a process independent Voltage and Current. This was now used for generating other types of biases as needed. Mainly it was used for a constant Gm bias. The idea was that this way, a single trimming will allow us to get an ideal of resistor corner on the chip and that information is reused elsewhere. This does not consider the mismatch of the devices across the different blocks across the chip. The spec wasn't that tight.
Click to expand...
Thank you nitishnu for your reply,

Indeed the PTAT behavioral is preferable for me, that is why I am using PTAT beta multiplier circuit.

While the BGR can offer us a reference voltage without trimming, it looks that is not possible for the current source, so there is no way of skipping trimming for it, at least for process dependency?
 

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Junus2012 said:
While the BGR can offer us a reference voltage without trimming, it looks that is not possible for the current source, so there is no way of skipping trimming for it, at least for process dependency?
Click to expand...

Something (RES/CAP/MOS/IND) will always vary with the process. So trimming is must for meeting accuracy.
Or you might need external components.

BTW, If your process has it and your accuracy requirements allow it, there might be passives with lesser variation across corners. Try the different flavors of resistors and see if any suits you better.
 
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