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Basic question on T lines

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vlsi_design2

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Hi,
T lines no matter how long they are, if properly terminated with ZL=Z0=R, always presents a resistive load and no capacitive load. Instead if I use a long trace of line of comparable dimension I get a huge capacitor with the substrate (say). Is there an intuitive way to understand this? or the best way is to rely on theoretical formula of Zin = f(Z0,ZL,tan(beta*l)) where once we substitute Z0=ZL, we see pure resistive input impedance?
How the huge cap magically disappears?
 

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One could ask the same thing about free space. It has a finite permittivity, how come the impedance seen by light or radio waves is generally real (resistive)?

The fact is the capacitance does not "disappear" -- it is simply balanced with the inherent inductance (permeability) to present a real characteristic impedance to the guided mode. If you have a length of line and don't terminate it properly, you have an imbalance of energy (i.e., capacitive or inductive) that causes a net reactance.
 
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The line behaves like cascaded LC segments, and you can model it like that.

It is not correct that long lines behave like capacitors. You would measured C into an open ended line, at low frequency. The general formula is more complex, because the line does impedance transformation if length becomes significant compared to your signals wavelength.

Narrow or wide lines all have L and C components and represent an instantaneous resistance to incoming signals. What varies is the value: lower for wide lines, higher for narrow lines.

If the line is lossless, line impedance is Zline = sqrt(L'/C')

rlcg.PNG
 
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