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limitation of Geometry Range Parameters of transistor

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r.mirtaji

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The length and width range specified for the transistor is as follows:
ADE/resualt/print/model parameter :

Wmax=10u Wmin=1.2u Lmax=350nm Lmin=130nm

I designed a simple circuit with a common source transistor And I put the length and width values out of range as follows

W=1u L=.5u

The simulator did not give any error message and the circuit was biased correctly.
Is not the length and width range of the transistor within the allowable range?!
I did the test again with the following value:

W=1m l=.5u

The simulator gave the following error message:

Error found by spectre during initial setup.
ERROR (CMI-2440): "input.scs" 15: M1: The length, width, or area of the instance does not fit the given lmax-lmin, wmax-wmin,
or areamax-areamin range for any model in the `nch' group. The channel width is 1.000000e-03 and length is 1.300000e-07
Click to expand...

Why the simulator indicates the allowable length and width range as above Wmax=900um Wmin=150nm Lmax=20um Lmin=130nm
What is the difference between the error value shown in the simulator and the model parameter at ADE/resualt/print/model parameter ?
 
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There could be 2 limit region.
-The region where the model is still valid
-The region where the manufacturability is in or out of.

It's PDK designer who specifies them. Simulator does not know.
 

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    r.mirtaji

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W you say is 1E-03 and Wmax is 900E-06 (9E-04) so seems to me it's doing its job insofar as the data it's been given.

A PDK strategy may be to warn at a value less than the reliability or manufacturability limits, and make you justify / beg before things get fuzzy / dicey.
 

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    r.mirtaji

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BigBoss said:
There could be 2 limit region.
-The region where the model is still valid
-The region where the manufacturability is in or out of.

It's PDK designer who specifies them. Simulator does not know.
Click to expand...
So what the CADENCE specifies as the length and width range of the transistor is from the part:
ADE/resualt/print/model parameter :
Wmax=10u Wmin=1.2u Lmax=350nm Lmin=130nm
The range that the manufacturer has the ability to build And outside this range the SPECTRE model is still properly simulated
 
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That last bit is not to be assumed, rather verified by PDK docs or your TPOC. The SRC or Spectre warning limits are for the foundry to hide behind but "why?" comes down to cases.
 

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