Would timing tool check this path?

It doesnt matter if C1/2 are 1,2 100 or 500 bits. Each output is still only a function of SEL, and 1 register is needed per bit.

Maybe a simple example will help clarify what others have been writing:

for example if c1 and c2 are:
c1 = 0110
c2 = 1011

then the mux (in verilog syntax)
always @(posedge clk) out <= sel ? c1 : c2;

the mux specifies the following and-or logic for generating out
out = sel & 0110 | ~sel & 1011;

expanding the logic to select each bit of the bus by the sel signal:
out = { sel & 0, sel & 1, sel & 1, sel & 0} |
{~sel & 1, ~sel & 0, ~sel & 1, ~sel & 1}
sel: invert, same, constant, invert

looking at each bit separatedly you can see that the following applies to each bit of out
this can be done using a truth table (in this case it's easy to see just written out)
out = {~sel, sel, 1, ~sel}

out is based entirely on sel or a constant there isn't a path from a c1 or c2 that exists in
the resulting circuit (after synthesis).

Thanks ads-ee,

That makes very good sense. What comes out from your reply is that after synthesis the constant values are translated direct to logic and no node exists as a separate constant.
Without considering synthesis I guess this doesn't apply. That is why I mentioned "away from tools or platforms".

I think others replied in a similar way but less direct as far as I see.

I am finally writing this recap if you don't mind.
The fact remains that when we say '0' or '1' as constants before synthesis or '0' & '1' after synthesis is really same concept. Only the diagrams may differ. Eventually they are wires connected to source or ground and entering the logic decision.

As such timing concepts still apply but since wiring to source/gnd is not a big deal and doesn't really need extra routing effort then I assume timing is going to be ok and nobody will need to care about defining such paths or not for assessment.
Thanks to all replies.