[HELP ME] [VHDL Code] Clk floating problem

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--library work;
--use work.all;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top_cpu1 is
    Port ( clk : in std_logic;
           start : in std_logic;
           reg_a_out : out std_logic_vector(4 downto 0);
           reg_b_out : out std_logic_vector(4 downto 0);
           reg_c_out : out std_logic_vector(7 downto 0));
end top_cpu1;

architecture Behavioral of top_cpu1 is

component ram256x8 is
	Generic ( bits: INTEGER := 8;
			words: INTEGER := 256);	
     Port (clk : in std_logic; 
		 ram_mar : in std_logic_vector(7 downto 0);
           ram_in : in  std_logic_vector(7 downto 0);
		 ram_out: out std_logic_vector(7 downto 0);
           ram_we : in std_logic);

end component;

component pc_reg is
    Port ( clk : in std_logic;
           pc_rst : in std_logic;
           pc_inc : in std_logic;
           pc_out : out std_logic_vector(7 downto 0));
end component;

component ir_reg is
    Port ( clk :in std_logic ;
    		 ir_in : in std_logic_vector(7 downto 0);
           ir_out : out std_logic_vector(7 downto 0);
           ir_we : in std_logic;
           ir_rst : in std_logic;
		 i_out : out std_logic_vector (3 downto 0));
end component;

component controlUnit is
--    Port ( u_inc : in std_logic;
--           u_rst : in std_logic;
--		 clk : in std_logic
--           pc_inc : out std_logic;
--           ir_we : out std_logic;
--           a_we : out std_logic;
--           b_we : out std_logic;
--           c_we : out std_logic;
--           ar_we : out std_logic;
--           addressB : out std_logic;
--           dataB0 : out std_logic;
--           dataB1 : out std_logic);
    Port ( clk : in std_logic;
    		 u_inc : in std_logic;
--    		 u_rst : in std_logic;
           istr_reg : in std_logic_vector (3 downto 0);
		 output_rom : out std_logic_vector (10 downto 0)

		 );
end component;

component c_reg is
    Port ( c_in : in std_logic_vector(4 downto 0);
           c_out : out std_logic_vector(7 downto 0);
           clk : in std_logic;
           c_we : in std_logic);
end component;

component data_bus is
    Port ( sel    : in std_logic_vector(1 downto 0);
    		 c_in   : in std_logic_vector(7 downto 0);
           mbr_in : in std_logic_vector(7 downto 0);
           ir_out : out std_logic_vector(7 downto 0);
		  a_out  : out std_logic_vector(7 downto 0);
		 b_out  : out std_logic_vector(7 downto 0);
		 mbr_out: out std_logic_vector(7 downto 0));
end component;

component address_bus is
    Port ( sel : in std_logic;
    		 pc_in : in std_logic_vector(7 downto 0);
           ir_in : in std_logic_vector(7 downto 0);
           mar : out std_logic_vector(7 downto 0));
end component;

component b_reg is
    Port ( b_in : in std_logic_vector(7 downto 0);
           b_out : out std_logic_vector(4 downto 0);
           clk : in std_logic;
           b_we : in std_logic);
end component;
component Alu is
    Port ( a_input : in std_logic_vector(4 downto 0);
           b_input : in std_logic_vector(4 downto 0);
           c_output : out std_logic_vector(4 downto 0));
end component;

component a_reg is
    Port ( a_in : in std_logic_vector(7 downto 0);
           a_out : out std_logic_vector(4 downto 0);
           clk : in std_logic;
           a_we : in std_logic);
end component;

signal clk1, NET1, NET2, NET3, NET4, NET5, NET6, NET7, NET8, NET9, NET10, NET11, NET12 : std_logic ;
signal BUS8_1, BUS8_2, BUS8_3, BUS8_4, BUS8_5, BUS8_6, BUS8_11, BUS8_12, BUS8_13  : std_logic_vector (7 downto 0);
signal BUS5_4, BUS5_5, BUS5_6 : std_logic_vector (4 downto 0);
signal BUS4 : std_logic_vector (3 downto 0);
signal BUS2_1 : std_logic_vector (1 downto 0);



begin
		
	  clk1 <= clk AND start;
	  BUS2_1 <= NET10 & NET11;
	  NET12 <= '1';

	  U1: pc_reg PORT MAP (clk => clk1, pc_rst => NET1, pc_inc => NET3, pc_out => BUS8_1);
	  U2: ir_reg PORT MAP (clk => clk1, ir_in => BUS8_4, ir_out => BUS8_2, ir_we => NET4, ir_rst => NET2, i_out => BUS4);
	  U3: controlUnit PORT MAP (clk => clk1, u_inc => NET12, istr_reg => BUS4, output_rom(10) => NET1,output_rom(9) => NET2,output_rom(8) => NET3,output_rom(7) => NET4,output_rom(6) => NET5,output_rom(5) => NET6,output_rom(4) => NET7,output_rom(3) => NET8,output_rom(2) => NET9,output_rom(1) => NET10,output_rom(0) =>  NET11);
	  U4: alu PORT MAP( a_input => BUS5_4, b_input => BUS5_5, c_output => BUS5_6);
	  U7: a_reg PORT MAP( a_in => BUS8_12, a_out => BUS5_4, clk => clk1, a_we => NET5);
	  U6: b_reg PORT MAP( b_in => BUS8_13, b_out => BUS5_5, clk => clk1, b_we => NET6);
	  U5: c_reg PORT MAP( c_in => BUS5_6, c_out => BUS8_11, clk => clk1, c_we => NET7);
	  U8: ram256x8 PORT MAP( clk => clk1, ram_mar => BUS8_3, ram_in => BUS8_5, ram_out => BUS8_6, ram_we => NET8);
	  U9: address_bus PORT MAP( sel => NET9 , pc_in => BUS8_1, ir_in => BUS8_2, mar => BUS8_3);
	  U10: data_bus PORT MAP( sel => BUS2_1 , c_in => BUS8_11, mbr_in => BUS8_6, ir_out => BUS8_4, a_out => BUS8_12 , b_out =>  BUS8_13, mbr_out => BUS8_5);
		


end Behavioral;