Caculating the wire length in Layout design for current density

Hello,

I have power stage amplifier that is drawing a static current 6 mA. I have MET1,2 with current density if 1mA/µm, so it was really looking wide connection of 6 µm width,
I am not sure if all designers keeps really this reliability consideration ?

More important for me, this stage is class AB, so in the transient the current will go higher, and if I wiuld design the wire length to the transient status then will be not acceptable layout at all

Thank you
Regards

Electromigration (EM) reliability is one of the most important considerations in IC layouts.
Good design styles put these requirements upfront, to create "correct by construction" layouts (if possible).
Also, there are specialized EDA tools, doing IR drop and EM verification - Totem, VoltusFi, etc.

For static currents only DC current densities should be checked.

For transient currents, usually three quantities are verified - average, RMS, and peak current densities.

timof said:

Electromigration (EM) reliability is one of the most important considerations in IC layouts.
Good design styles put these requirements upfront, to create "correct by construction" layouts (if possible).
Also, there are specialized EDA tools, doing IR drop and EM verification - Totem, VoltusFi, etc.

For static currents only DC current densities should be checked.

For transient currents, usually three quantities are verified - average, RMS, and peak current densities.

Click to expand...

Thank you for your nice answer,

I found the current density information from the data sheet, but those couldnt find (average, RMS, and peak current densities) or may it have different abbreviation.

I am using Cadence design tools, where I can check for reliability?

Your PDK should come with electrical design rule manual, that should contain all that information.
If it's missing, well, maybe foundry did not care to provide that, or in that technology no one care to check the current densities for dynamic problems.
You can always schek with your foundry.

What technology node are you working with?

Cadence has several tools helping to verify and design for current density - EAD (Electrically Aware Design), VoltusFi (IE / EM analysis for transistor-level designs), Voltus (IR / EM for gate level), etc.

There are also other EDA vendors providing IR / EM analysis tools - you can mix and match, it's interoperable, with standard interfaces (like DSPF or SPEF files, etc.).

There are also smaller EDA vendors, that offer alternative, and often very good solutions for IR / EM analysis.

In simple cases, when you have one or few wires / metal lines and vias in your design, you can check manually or visually, for current density.

In most of the practical and commerical designs, though, the layouts are so complex that it is absoluely impossible to check IR / EM manually, and you need to use EDA tools for that.

Voltus-FI or Layout EXL. However, you need a proper setup files for given process. It is possible to create custom setup as well, but need data of course.

In old process the way was to ensure that path width mets constraints for max dc density +some margin. And it was Arbitrarily decision of designer.

Usually, fab will provide formula to calculate this stuff, make a spreadsheet for this calculation.
I personally margin up 10-20% depend on case for calculation. The only tricky part of this way is choosing the most appropriate resistance path.
Then you can verify by Totem or Voltus.

Another way to check on the fly is using EAD (extra lic) if you IC6.18, or Custom compiler also provide tool (don't quite remember the name) with same function with free of charge.