Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Calibre LVS error port not matched

Status
Not open for further replies.

amiramu10

Newbie level 4
Joined
Oct 21, 2015
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,423
I have seen previous solution to this but could not find the correct and exact answer. Kindly see the attached pictures for clarity. I am using umc180nm technology. Ports in schematic and layouts are not matched. I have made all the labels and pins in layout.
 

Attachments

  • 2021-02-22 (7).png
    2021-02-22 (7).png
    190.4 KB · Views: 302
  • 2021-02-22 (6).png
    2021-02-22 (6).png
    196.1 KB · Views: 197

I saw many people asking the same question. But now I have solved the problem. The answer lies in defining the labels. When we define labels for each pin then we have to select material of label carefully. Though it is technology dependent and varies with the fdk/pdk. But the solution is there. So remember it would be something related to "Text" . In my case, UMC180nm, this is solved by choosing ME1-CAD-Text from the many materials available for text label. For other, it may be "ctext". There are many guessed answers in but none of them works. This is the final and practiced answer.
 

It's not just "text layer".
It should be text layer that is "attached" to proper metal layer, and designated as port layer.
(In Virtuoso, it's usually called "pin layer").
And this text label (normally) should be placed in the upper cell hierarchy.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top