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[SOLVED] Problem with synchronous clock

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VerLearn

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I have a question where I need to stay for certain amount of time looping in the code. I'm facing the problem of applying the clock to the circuit.

Example:

module
................ ................
always@(posedge clk) begin
case()
s0: begin
...................
for(i=0;i<100;i=i+1) begin
.................. ..................
end
s0: begin
...................
for(i=0;i<20;i=i+1) begin
.................. ..................
end
s0: begin
...................
for(i=0;i<100;i=i+1) begin
.................. ..................
end
s0: begin
...................
for(i=0;i<20;i=i+1) begin
...................................
end
endcase
end
endmodule

For the above circuit, how do I provide synchronous clock?
1. I should execute my first loop for exactly 100 times and display the output.
2. I should execute my second loop for exactly 20 times and display the output.
3. I should execute my third loop for exactly 100 times and display the output.
4. I should execute my fourth loop for exactly 20 times and display the output.

Please help, thanks in advance.
 

You pseudo-code looks weird......All your case names are same : s0
Where is your original code, do you have one and if so, have you compiled it? Do post it here for better debugging. Remember the compiler is your first and best friend.

I did not exactly understand the question. You want to stay in a certain state for a certain amount of time and then exit the state?
If this is so, then do not use a for loop. Use a up-counter which increments on every rising edge of the system clock and when the desired no. of iterations (time) has been reached then transit to another state.

I'm facing the problem of applying the clock to the circuit.
Click to expand...

Why? clk looks like the clock signal and a port should be providing it.

btw - It also looks like this post is duplicated in the Xillinx forums!
 
Last edited:
VerLearn said:
I have a question where I need to stay for certain amount of time looping in the code. I'm facing the problem of applying the clock to the circuit.
For the above circuit, how do I provide synchronous clock?
Click to expand...
You already had a clock for the pseudo code. Everything after the always @(posedge clk) is considered to be synchronized to the clock edge.
Code: 
module
//.......
always@(posedge clk) begin  // this applies the clock (i.e. makes code between these two lines syncrhonous)
end
//........
endmodule

Given you used a combination of pseudo code (for loops) and synthesizable code (always)...I'm thinking you've only written software in the past. Don't think of Verilog as software, it models hardware. So think of how the circuit has to work and then write the code to model that circuit.
 
Thank you so much for the reply.

Using loops and always together is not a good coding practice. I agree.

Now, think of a situation where I need to count in two case constructs that are sensitized to the positive edge of the clock. In the first construct, I need to count to 100, and I need to count to 20 in the next construct.(Assume that state is directed to the next state after executing the present state) What should be my clock period?

If I use,
always #50 clk=~clk; (Assume that the clock is initialized to zero)

AT t=50, when rising edge is detected, always construct executes, and the first case in the construct is executed. It counts to 100 with #1 delay, and the state changes to the next state. Now, t=150.
At t=150, when the next rising edge is detected, second case gets executed where it counts to 20 with #1 delay. The state changes to the next state. Now, t=170.

My problem is, it remains idle till the next rising edge is detected i.e, till t=250, but the next state should start executing at t=170. How do I code this? I tried to be as simpler as possible.

Please help.
thanks a ton in advance
 

Don't mix up simulation timing statements with clocked delays.

I understand that you are asking about clocked delays in real hardware.

A state machine with delay could look like this
Code: 
always @(posedge clk) begin
case (state)
s0: begin
  state <= s1;
  cnt <= 50;
end;
s1: begin
  if (cnt)
    cnt--;
  else
    state <= s2;
end;
s2:
end;
 
To elaborate on FvM's post when you count you are clocking the counter that is doing the counting. It isn't a clock edge is seen in a state and then somehow you count without a clock for 100 counts...you clock the counter until it reaches a terminal count value which causes it to go to the next state like shown in FvM's code snippet.
 
ads-ee said:
To elaborate on FvM's post when you count you are clocking the counter that is doing the counting. It isn't a clock edge is seen in a state and then somehow you count without a clock for 100 counts...you clock the counter until it reaches a terminal count value which causes it to go to the next state like shown in FvM's code snippet.
Click to expand...
So, should I use rising edges of the clock for counting? I think that solves the problem, doesn't it?

Thanks in advance.
 

FvM said:
Don't mix up simulation timing statements with clocked delays.

I understand that you are asking about clocked delays in real hardware.

A state machine with delay could look like this
Code: 
always @(posedge clk) begin
case (state)
s0: begin
  state <= s1;
  cnt <= 50;
end;
s1: begin
  if (cnt)
    cnt--;
  else
    state <= s2;
end;
s2:
end;
Click to expand...
Your answer really helped me in looking at a problem in a different way(synthesis). I have been coding using #delays without having the sense that they can't be synthesized. In this problem, if I use edges of the clock for counting, I think I should do good.

Please suggest how to adapt to coding that can be synthesized. Suggest the simulation tool as well.

Thanks a ton in advance.
 

I serached "Verilog for synthesis" and there are online info as well as books. Read the one of your choice. Study the ones created/written after 2015.

Suggest the simulation tool as well.
Click to expand...
Paid or free?
I would suggest Modelsim Student Edition (SE) version as a stand alone simulator if your target is just to simulate the HDL code.
There are also FPGA tool chain bundles from Xilinx/AMD(Vivado), Microsemi(Libero SoC), Intel, etc which have their own free-version of simulator along with synthesis and placement tools.
 
Last edited:
dpaul said:
You pseudo-code looks weird......All your case names are same : s0
Where is your original code, do you have one and if so, have you compiled it? Do post it here for better debugging. Remember the compiler is your first and best friend.

I did not exactly understand the question. You want to stay in a certain state for a certain amount of time and then exit the state?
If this is so, then do not use a for loop. Use a up-counter which increments on every rising edge of the system clock and when the desired no. of iterations (time) has been reached then transit to another state.


Why? clk looks like the clock signal and a port should be providing it.

btw - It also looks like this post is duplicated in the Xillinx forums!
Click to expand...
Thanks for the reply.
Actually, it should be s0,s1,s2,s3. That was a mistake. Using loop and always construct is not at all a good coding practice. I came to know it very recently(after posting the thread). I used to code to get the required answer from the monitor. Now, my view on Verilog code had changed a bit. Whatever I write, I'm trying to map it digital hardware. Thanks a lot. It helped me.
--- Updated ---

VerLearn said:
Thanks for the reply.
Actually, it should be s0,s1,s2,s3. That was a mistake. Using loop and always construct is not at all a good coding practice. I came to know it very recently(after posting the thread). I used to code to get the required answer from the monitor. Now, my view on Verilog code had changed a bit. Whatever I write, I'm trying to map it digital hardware. Thanks a lot. It helped me.
Click to expand...
I posted the same question in the xilinx forums as well. I did it to get the maximum reach of the solution. Was it against the forum rules?
 

VerLearn said:
I posted the same question in the xilinx forums as well. I did it to get the maximum reach of the solution. Was it against the forum rules?
Click to expand...
Not against forum rules, but it doesn't respect a forum members time spent answering your questions, which may have already been answered by a member on another site. Those members who predominately answer questions do so voluntarily and are not paid for their efforts.

Cross posting on this forum is not allowed as not all members watch all forum sections nor do members on this forum necessarily visit or have accounts on other forums. Overall cross posting questions on forums is frowned upon by many forum users.
 
ads-ee said:
Not against forum rules, but it doesn't respect a forum members time spent answering your questions, which may have already been answered by a member on another site. Those members who predominately answer questions do so voluntarily and are not paid for their efforts.

Cross posting on this forum is not allowed as not all members watch all forum sections nor do members on this forum necessarily visit or have accounts on other forums. Overall cross posting questions on forums is frowned upon by many forum users.
Click to expand...

Thanks a lot for letting me know.
I didn't think so much before doing it. I won't repeat it.
 

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