Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

some ads problem about convergence substrate error

Status
Not open for further replies.
D

Dummyeng

Member level 4
Joined
Mar 25, 2018
Messages
78
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
431
i design an amplifier but its give me some error and warnings like
First this warning happen and i dont know why
Warning detected by hpeesofsim in Substrate model during netlist flattening.
Simulations referencing substrate `MSub1' will not include metal loss
because metal thickness is zero.
i think i give correct number
1.jpg
and second problem is that ads reject some number

Fwd sourceLevel=807.661e-03 80.77% 2/2 Step=121.9047619 rejected

Fwd sourceLevel=682.979e-03 68.30% 2/2 Step=58.04988662 rejected

and in the end it happnd

2.jpg


and
 

There is nothing with Substrate.It's a Convergence Problem coming from your Layout and/or Port Configuration.
 

    D

    Dummyeng

    Points: 2
    Helpful Answer Positive Rating
In your substrate block, you have defined metal thickness T=0 mil
 

    D

    Dummyeng

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top