Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

clock for "input reg"

Status
Not open for further replies.
fran6

fran6

Newbie level 4
Joined
May 2, 2005
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,337
Hello,

When I wanted to have a value latched in a module, I have always done:

Code: 
module my_module(clk, myinput);
    input wire clk;
    input wire myinput;
    
    reg latch_myinput;

    always @(posedge clk)
    begin
        latch_myinput = myinput;
    end
endmodule

With the above code, it is clear that the input is latched synchronously to the clock clk.
An other way to latch an input is to declare myinput as "input reg":

Code: 
module my_module(clk, myinput);
    input wire clk;
    input reg myinput;
endmodule

I am wondering when the value of myinput is updated ? Which clock is used to supply this register ?

regards,
Fran6
 

Have you tried compiling your second method ... I use modelsim and no it does not compile and gives port mode incompatible with declaration ... which is rightly so !

My understanding of declaring a port as wire or reg is very simple ... if you are going to assign a value in initial / always block use reg else use wire .

No Input can ever be assinged so no point in declaring that as a reg it is always wire .
Synthesis tool has very little concern with reg/wire .. it is bascially more helpful to the simualtor . If you disagree with me please do mail me back :)
 

    fran6

    fran6

    Points: 2
    Helpful Answer Positive Rating
This is usually a bug:
latch_myinput = myinput;

Do this instead:
latch_myinput <= myinput;

A Verilog input port cannot be a register. This is an error:
input reg myinput;

You may want to choose a different register name. The word "latch" suggests level-sensitive.
 

    fran6

    fran6

    Points: 2
    Helpful Answer Positive Rating
the "input reg" synthesize with Quartus but you are both right, is doesn't make any sense.
thanks.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top