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Power dissipation calculation for FPGA-ADC interface

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matrixofdynamism

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An FPGA can be interfaced with an ADC using CMOS or LVDS. Is there a way to use simulation to predict the power dissipation of the I/O blocks for a given operating frequency for this interface? If so, how can this be carried out?

Here we have an Intel MAX 10 and a Microsemi IGLOO2 being linked to a TI ADC. It would be great to be able to get a very reliable estimate for power dissipation between these two FPGAs when using LVDS and also when using CMOS, to interface with the TI ADC.
 

I don’t know if you can do this in simulation, but it should be a straightforward calculation as long as you know the frequency, static and dynamic(capacitive) load.

i don’t think there should be much difference between devices; LVDS is LVDS.
 

LVDS is used in both places but the current drive strength will be different between the two devices. If a simulation is carried out, it will be a more reliable estimate basically because the simulation will use the I/O buffer models for the FPGA and the ADC and also the PCB track information.
 

I disagree. LVDS outputs are current sources terminated by 100 ohms. By specification, that current has to be within a certain range.
 
The LVDS signal is supposed to have about 350 mV of swing between the high and low values with an offset from ground that depends somewhat on the voltage used for the IO bank. So the current is very low and depends on the frequency of the transfer and will nearly indentical across multiple vendors.
 
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