matrixofdynamism
Advanced Member level 2
An FPGA can be interfaced with an ADC using CMOS or LVDS. Is there a way to use simulation to predict the power dissipation of the I/O blocks for a given operating frequency for this interface? If so, how can this be carried out?
Here we have an Intel MAX 10 and a Microsemi IGLOO2 being linked to a TI ADC. It would be great to be able to get a very reliable estimate for power dissipation between these two FPGAs when using LVDS and also when using CMOS, to interface with the TI ADC.
Here we have an Intel MAX 10 and a Microsemi IGLOO2 being linked to a TI ADC. It would be great to be able to get a very reliable estimate for power dissipation between these two FPGAs when using LVDS and also when using CMOS, to interface with the TI ADC.