neycalazans
Newbie
I am interested in using and developing transistor sizing tools for digital design, either for creating specific standard cell libraries and/or to produce a sized digital transistor network for CMOS technologies.
Does anyone knows about commercial or open source tools to perform transistor sizing for CMOS digital networks?
We have developed some in-house approaches for automatically sizing transistors in my research group (a combination of sizing heuristics and also software to perform sizing according to some performance/power/size criteria), and we would like to compare our heuristic/tools results with other approaches.
I can find many publications in the literature about transistor sizing in the sense I explained above, but no link to specific tools available.
We have access to Cadence, Synopsys and Mentor University programs, but I could not find a sizing tool or even some embedded sizing functionality into some tool from these vendors. We are used to design ASICs using standard cell libraries where differently sized gates already exist and are employed by synthesis tools like Cadence genus or Synopsys DC. But we do need to create our own gates or transistor networks in general, and we know the effect of transistor sizing is significant on the final circuit.
Ney
Does anyone knows about commercial or open source tools to perform transistor sizing for CMOS digital networks?
We have developed some in-house approaches for automatically sizing transistors in my research group (a combination of sizing heuristics and also software to perform sizing according to some performance/power/size criteria), and we would like to compare our heuristic/tools results with other approaches.
I can find many publications in the literature about transistor sizing in the sense I explained above, but no link to specific tools available.
We have access to Cadence, Synopsys and Mentor University programs, but I could not find a sizing tool or even some embedded sizing functionality into some tool from these vendors. We are used to design ASICs using standard cell libraries where differently sized gates already exist and are employed by synthesis tools like Cadence genus or Synopsys DC. But we do need to create our own gates or transistor networks in general, and we know the effect of transistor sizing is significant on the final circuit.
Ney