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Single Reset in Async FIFO - how to use? What clock domain connect to?

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ivlsi

ivlsi

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Hi All,

An Async FIFO has two clocks, but a single reset. Where/how to connect this single reset (what clock domain)? Is a single reset enough?

Thank you!
 

it is entirely possible the FIFO is implemented with flops that have async reset themselves. if they are async, they are async to any clock. the FIFO could have 3 clocks, 10 clocks, it wouldn't matter.
 

    ivlsi

    ivlsi

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should the clocks be gated so they will start after de-assertion of the reset in order to eliminate the metability?
As for as I know, using the async reset may bring to the logical errors ... So, how to use the async reset on the safe side? stop the clocks during the reset?
 

ivlsi said:
should the clocks be gated so they will start after de-assertion of the reset in order to eliminate the metability?
As for as I know, using the async reset may bring to the logical errors ... So, how to use the async reset on the safe side? stop the clocks during the reset?
Click to expand...
I believe a properly designed flip flop can do this for you such that you don't have to worry about it at FIFO or higher level.

do you have such low level information to crosscheck?
 

"properly designed flip flop can do this for you" - the timing of clock and reset is defined externally to the flop... so how could it handle internally? the clock & reset can rise/fall close one to another, so removal/recovery violations may happen.
What is crosscheck? could you explain, please?
 

I meant, can you verify what flops your fifo is using? do you have access to low level implementation details?
 

I can choose the flops type ... For FIFO itself I have chosen FlipFlops without reset. As for the around logic - FlipFlops with the reset. But there is only one reset pin but two clock domains... So, if I want to synchronize the reset, so for which clock domain? write side? read side? slowest clock? fastest clock? provide it asynchronous to two clock domains?
 

if the flops have async reset, you don't need to synchronize with anything. this seems like the easiest solution to me. maybe i am missing something?

otherwise we would be arguing about who synchronizes the synchronizer that synchronizes the fifo.
 

what's going on when there is a removal/recovery violation? how to solve in FPGA? ASIC?
 

Have you checked with the vendor to see if the FIFO locally synchronizes the asynchronous reset input to both clock domains internally?

The last time I worked on an ASIC (10+ years ago) the dual clock FIFO we used only had a single asynchronous reset and that reset was synchronized to both clock domains in the FIFO core.

I've also seen this done on FIFO cores from FPGA vendors.
 

    ivlsi

    ivlsi

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