Simulation for offset voltage of clocked comparator.

clocked comparator

Hi everyone,

I am designing a high speed clocked comparator. Now i want to simulate for offset voltage using HSpice. I use syntac .dc Vinput 0 3.3 1m.

If i were to simulate for offset voltage of a normal comparator, the simulation works fine. But I encounter problem when i want to simulate a clocked comparator using HSpice. I couldn't get the DC transfer characteristics of an output voltage. Can anyone tell me this happen? Can someone tell me how to simulate for offset voltage of high speed comparator using HSpice?

cheers

comparator input offset voltage

Perform transient MC simulations as with s fixed input voltage which you sweep from say -20mv to 20mV in steps of 5mV. Then for each input voltage, you perform a comparing cycle. So, at the end of the simulation you will be able to determine the input range for wich your comparator allways gives a HIGH or a LOW on its output. Once you determined that the negative offset is between, say, -15mV and -10mV, you could repeat the procedure with steps of 1mV. The same for the positive offset.

.extract tran

Hi humungus,

Thanks for the note. I still don't understand the method you explained. Could you elaborate more and explain the steps a bit more details. What is the syntax i need to use for transient MC to measure offset voltage of a high speed comparator? Do you know any good reading reference on this topic?

thanks alot

comparator offset simulation

1) Set one comparator input to a reference voltage. Use a PWL source to set the varying comparator input voltage.
2) Use a parameter as value of the input voltage.
3) Write the statements to perform a transient simulation of one conversion cycle. You must start your simulation by applying an input voltage so that you know the state at the output of your comparator. Then, in the simulation your PWL source applies the input voltage you want to test. You must also set a clock signal.
4) Write the statement to perform a sweep of the input voltage parameter.
5) Write the statements to perform N MC simulations for every sweep step. In eldo, that is made by means of the keyword "OUTER" in the MC statement.
6) Extract the result of the comparison at a time where you know all transistions have stoped.
7) Plot the result of the extract versus the input voltage parameter (see attached figure)

Then, in the figure you can see that the input offset voltage is 25mV.

I you found this post usefull, do not forget to push the "Helped me" button;-)

******* Control sources
** Main clock
Vck ck 0 5 PULSE 5 0 0 10e-9 10e-9 'parbit_time/2-10e-9' 'parbit_time'

***** Clock parameters
.param parbit_time=0.5e-6

** Comparator reference
Vref_mid vref_mid 0 2.5

******* Input voltage
.param paramvin=5
Vin vin 0 0 PWL 0 0
+ '0.75*parbit_time' 0 '0.75*parbit_time+10e-9' 0
+ '1.75*parbit_time' 0 '1.75*parbit_time+10e-9' paramvin
+ '2.75*parbit_time' paramvin '2.75*parbit_time+10e-9' 0

******* Simulation statements
.tran 5e-9 '3*parbit_time' 0.4e-6 10e-9 uic
.step PARAM paramvin 2.45 2.55 5e-3
.mc 200 outer v(q_cmp) all

****** Extraction statements
.extract tran label=cmpout valat(v(q_cmp), at='2.75*parbit_time')

I would recommend a slow ramp input instead of using stepped simulations. This applies for unclocked comparators too. Simply because it's more efficient to measure offset via a single transient with (an extremely) slow-ramp input, rather than running N DC simulations. For high gain comparators, to get a reasonable accurate reading requires a huge N. Not forgetting that for MC simulations, you have to multiply the simulation count by 1000 times or more, depending on how many sigma you are designing for.

Added : In fact, you can do a slow rising ramp and falling ramp, and with some plotting tricks, even obtain a hysteresis curve with a single transient.