Simulation of output stage

I have implemented a two stage ota with class AB output. I need help in simulating the required plot. Kindly anyone help me.

Try the free LTspice download from Analog Devices.

Your output Mosfets are source-followers that have a high gate-source voltage to turn on so the amplifier will produce a low voltage output signal. Look at the schematic of any Cmos amplifier IC to see that the output Mosfets are not source-followers, instead they are in a common source design that allows a rail-to-rail output voltage swing.

To get that characteristic the load should be connected to a mid-rail voltage (VDD/2), not to ground. Common-drain output stage is used usually with dual-supply, positive and negative source (VDD and VSS). In your case always the upper MOS will conduct.

Yeah, but I have task to implement Class AB push pull output stage and hence my Voltage swing will be limited roughly by VDD-0.3 to VSS+0.3.

bharath_k said:

Yeah, but I have task to implement Class AB push pull output stage and hence my Voltage swing will be limited roughly by VDD-0.3 to VSS+0.3.

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Absolutely not!
Your source-follower (common drain) Mosfets are used differently than used in Cmos opamps and Cmos audio amplifiers that use common source output devices. Your method is used with bipolar transistors that have a small 0.7V base-to emitter voltage drop so their output swing can be within 1V or 2V from each supply voltage. Your Mosfets might have a 4V gate to source voltage drop which means the output cannot swing closer than 4V to 5V to each supply.

Here is the description of a Texas instruments OPA2348 Cmos rail-to-rail opamp that can swing its output to within 18mV to 100mV from each supply rail:

Here is the architecture given to me.

you can plot I-V curve in the keysight ADS as well.

Your output transistors are common-drain that will not work with enhancement Mosfets. Who gave you architecture that will not work?
Look at the hundreds of schematics of Cmos opamps and Cmos audio amplifiers in Google images to see that they ALL use common source Mosfets at the output.

Okay I will reconfirm with my supervisor and check for different architecture.

Here is a circuit that uses ordinary transistors at the output that are common-collector emitter followers. But your circuit is using Mosfets that are completely different to ordinary transistors.

Audioguru, the MOSFETs of a CMOS process kit is completely else than a discrete device which is designed to tolerate x*10V Vds and y*1A Ids. In integrated circuits the threshold voltage variation is much smaller. A commonly used 180nm process for example contains 3.3V devices with Vth variation of 0.6V to 0.9V, Vth variation of 1.8V core devices even smaller, like 0.4V to 0.6V. I am sure they won't have 4V Vgs with proper design, they can even operate in subthreshold region. PDKs contain low-threshold devices too, extra cost sometimes, but not impossible to work with them.

Hi Frank,
You and others talk about the threshold voltage of a Mosfet input for it to be active, but the threshold voltage is when the current in a Mosfet is so low that it is almost turned off.
I do not design and build Cmos ICs, instead I just buy one. All the Cmos amplifier ICs that I have seen are rail-to-rail then their output Mosfets are common source, not common drain as in the schematic posted.

Audioguru said:

the threshold voltage is when the current in a Mosfet is so low that it is almost turned off.

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Still, these are not discrete devices. CMOS bias currents regurarly not bigger than 100uA for a standard OPAmp. With low length (~200nm) and not too big width (~10-100um) a device can conduct easily this 100uA under the threshold voltage, but close to the threshold. If the W/L for the device is such large as above a very small gate-overdrive voltage is needed to reach even much higher currents. In sub-threshold conduction the Ids(Vgs) function is exponential, over Vth it is a square-law function, thus Ids arises rapidly close to the Vth, especially under it.

Audioguru said:

All the Cmos amplifier ICs that I have seen are rail-to-rail then their output Mosfets are common source, not common drain as in the schematic posted.

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I believe for you, I haven't seen too much. I can imagine that standard discrete OPAmps have to operate with at least 10V supply, otherwise manufacturers couldn't sell enough. With higher supply the devices have to tolerate higher voltages, Vth variation is higher and they cannot ensure the desired output voltage range with common-drain output then. But this is not that case, bharath_k is designing for 22nm technology and 1.8V supply. He started other posts in this topic, unfortunately he didn't share these infos here.

Most Cmos rail-to-rail opamps work with a 5V supply 5.5V maximum). It is too bad that miniscule chip size, voltages and currents were not mentioned by Bharath.
I found these things in Google: