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ask for reference design of CMOS RF transistor layout

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rficlover

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currently I am doing design on the current starved VCO, which is a series of current controlled inverters.
I use 2.5u width finger.
The current transitor layout make the cell not compact, and the interconnections between the delay cells are two long.
I would like to know how to design the transistor layout and how to place them in order to shorten the interconnection distance, so that the parasitic will be lower.
thanks all.
 

there are usefull and efficient softwares which are designing the cmos layout by consideration of all points u mentioned. layout with the best placement and most efficient routing. hspice has such automatic layout designer but not very graphical.
i used protel and orcad to some extent but hspice has more options.
 

    R

    rficlover

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currently i am using Cadence IC. I do not know how to generate layout from schematic.
The others told me that I have to draw the transistors and place them and connect them one by one. And I am following the advice.
However, I am still lack of layout skills, and do not know how to layout transistors efficiently and compact.
The books about layout do give some hints, however, it is not easy to quickly learn the hints from the thick books:)
So I would like to just follow the design of some experienced ones.
 

Most of the know how to are come from experience.
Maybe you can find some materials from the big company like IT or ADI internally. The best-rated book for layout rightnow is "The Art of Analog Layout"
 

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    rficlover

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looks like you're having trouble from interconnect parasitic. I hate to tell you this but you can't find a book that'll teach you these things. It's a function of time. I used to suck at layout myself but with time I got better. I took a long time to learn because my geometrical sense is really bad. If I can learn it with time, so can you. Just keep trying different ways and extract them and find which way you can save few aF of parasitic caps!
 

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    rficlover

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i find that the extract function from the Virtuoso can not extract the parasitics of R and C at the same time, also it can not extract the L.
I would like to know how you extract the full parasitics, including the interconnection metal lines (it should be treated as transmission line).
 

    R

    rficlover

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rficlover said:
currently I am doing design on the current starved VCO, which is a series of current controlled inverters.
I use 2.5u width finger.
The current transitor layout make the cell not compact, and the interconnections between the delay cells are two long.
I would like to know how to design the transistor layout and how to place them in order to shorten the interconnection distance, so that the parasitic will be lower.
thanks all.
Click to expand...

Refer to the TSMC pcell, you can find it.
 

rficlover said:
currently i am using Cadence IC. I do not know how to generate layout from schematic.
Click to expand...
In the schematic editor, do Tools/Design Synthesis/Layout XL
In the layout window, Design/Gen from Source

You just then need to place the components and route them.

Added after 52 seconds:

beabroad said:
i find that the extract function from the Virtuoso can not extract the parasitics of R and C at the same time, also it can not extract the L.
I would like to know how you extract the full parasitics, including the interconnection metal lines (it should be treated as transmission line).
Click to expand...
You should be able to. Are you using Assura? One of the options allows you to specify to extract RCL.
 

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