shanmei
Advanced Member level 1
Dummy cell for the input differential pair of opamp
In 1, the plot is a layout of pMOS transistor without dummy transistor, only 2 figures are shown for demonstration.
In 2, main transistor: (D is composed of DA and DB, S is composed of SA and SB, G is composed of GA and GB).
Dummy transistor: All terminals(D1,S1,G1 and B1) (D2,S2,G2 and B2) of the dummy transistor should be short to Vdd. In order to reduce the mismatch, the same layout environment is made for the layout, but D1 active region is short to D active region, which is not right.
In 3, D1 and D is not connected. However, there is no same layout environment for the main transistor, since there is a gap there. For example, the SA and SB have different neigboring figures, which is not a good match.
How should I place the dummy transistor? Thanks.
In 1, the plot is a layout of pMOS transistor without dummy transistor, only 2 figures are shown for demonstration.
In 2, main transistor: (D is composed of DA and DB, S is composed of SA and SB, G is composed of GA and GB).
Dummy transistor: All terminals(D1,S1,G1 and B1) (D2,S2,G2 and B2) of the dummy transistor should be short to Vdd. In order to reduce the mismatch, the same layout environment is made for the layout, but D1 active region is short to D active region, which is not right.
In 3, D1 and D is not connected. However, there is no same layout environment for the main transistor, since there is a gap there. For example, the SA and SB have different neigboring figures, which is not a good match.
How should I place the dummy transistor? Thanks.
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