Editing synthesised RTL in cadence virtuoso

Can I edit in the Synthesised RTL (got from Design Compiler) in cadence virtuoso ? ...like adding some new cells/pins manually and then go to encounter for P&R ?

Another question, Can I simulate an imported layout in cadence virtuoso without schematic (netlist) ?

A netlist (Synthesized RTL) is just a text file - so you can edit it in any text editor, including Virtuoso's.

No, you can simulate a layout directly. You need to either extract a netlist from the layout using an extraction tool (or just export the corrsponding netlist from Encounter - although that wont have parasitics)

jbeniston said:

A netlist (Synthesized RTL) is just a text file - so you can edit it in any text editor, including Virtuoso's.

No, you can simulate a layout directly. You need to either extract a netlist from the layout using an extraction tool (or just export the corrsponding netlist from Encounter - although that wont have parasitics)

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How can I a netlist include the effect of parasitics, I think if I want to simulate the design with effect of parasitics I should import the SPEF file (generated from encounter) which has all layout parasitics or extract the parasitics in virtuoso from imported GDSII and include it in simulation. Please correct me if I'm wrong.

Thanks

I meant to say "No, you can't simulate a layout directly".

There are two approaches - either export Verilog netlist + SDF from Encounter and simulate in ModelSim/Incisive.

Or, extract a spice netlist from the GDSII and simulate in HSpice/Spectre.

jbeniston said:

I meant to say "No, you can't simulate a layout directly"

Click to expand...

1) Yes, I know that. I was commenting on your statement "You need to either extract a netlist from the layout using an extraction tool (or just export the corrsponding netlist from Encounter - although that wont have parasitics)" so I was wondering how can a netlist include the parasitics ? (Will it model each interconnect wire as a lumped RC model and include coupling capacitance as an explicit capacitor ?)

2) How can I extract netlist from GDSII ?...Can I do that using SoC encounter ?

3) I'm designing a VLSI layout that has digital input streams and two kind of outputs: a digital output stream and an analog output signal. Can I simulate such design in HSpice or Spectre?

Thanks

For purely digital simulation, from Encounter, you would run rc extraction from within Encounter - and this will allow you to output a SDF file and Verilog netlist you can simulate in ModelSim/Incisive. (You can also generate a SPEF if you want to look at the RCs, but you need a SDF for simulation).

For analog simulation, you need to extract a spice netlist from your GDSII, using Cadence QRC / Synopsys Star RC / Mentor Calibre xRC, then sim in hspice/spectre

jbeniston said:

For purely digital simulation, from Encounter, you would run rc extraction from within Encounter - and this will allow you to output a SDF file and Verilog netlist you can simulate in ModelSim/Incisive. (You can also generate a SPEF if you want to look at the RCs, but you need a SDF for simulation).

For analog simulation, you need to extract a spice netlist from your GDSII, using Cadence QRC / Synopsys Star RC / Mentor Calibre xRC, then sim in hspice/spectre

Click to expand...

Thank you for your reply. But for the analog simulation, I have to enter a digital input stream to have the output analog signal, is this possible in HSpice/Spectre ?

You could try using a piecewise linear (PWL) voltage source, if in pure spice - or use Verilog-A.

oAwad said:

Thank you for your reply. But for the analog simulation, I have to enter a digital input stream to have the output analog signal, is this possible in HSpice/Spectre ?

Click to expand...

Yes, it is. There are many ways to get it done, including using a testbench written in verilog.

ThisIsNotSam said:

Yes, it is. There are many ways to get it done, including using a testbench written in verilog.

Click to expand...

I once read that verilog testbench simulation is used to test only the functionality of digital circuits and can't simulate transient effects or output analog signals (in case of my design)...please correct me if I'm wrong.

- - - Updated - - -

jbeniston said:

For purely digital simulation, from Encounter, you would run rc extraction from within Encounter - and this will allow you to output a SDF file and Verilog netlist you can simulate in ModelSim/Incisive. (You can also generate a SPEF if you want to look at the RCs, but you need a SDF for simulation).

For analog simulation, you need to extract a spice netlist from your GDSII, using Cadence QRC / Synopsys Star RC / Mentor Calibre xRC, then sim in hspice/spectre

Click to expand...

1) Can the analog simulation on spectre output the digital stream as well ? (I want to place the output digital stream and the output analog signal on the same graph vs time).

2) Is there a way to generate the Spice netlist file from within Encounter (using QRC standalone extraction) ? .....or I have to transfer the GDSII to Virtuoso and extract the Spice file from there using Cadence QRC ?

In Encounter's QRC standalone extraction, I see that I can use LEF files only without GDS (as in attached file)...so can I generate Spice file with LEF and verilog netlist only ?



* Should I provide the CapTable file in any of these steps if I have it from the PDK provider?

jbeniston said:

You could try using a piecewise linear (PWL) voltage source, if in pure spice - or use Verilog-A.

Click to expand...

1) Can I enter the input digital stream using verilog testbench ?


Thank you! and sorry for too many questions

You are so so lost. Mixing so many concepts in one post.

ThisIsNotSam said:

You are so so lost. Mixing so many concepts in one post.

Click to expand...

Can you please try to elaborate my misconceptions or direct me to some resources ? as I'm totally new to that. Thanks