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Same Problem(Width mismatch. Expected width 8, Actual width is 3 for dimension 1 of D
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_LOGIC_arith.ALL; use IEEE.std_logic_unsigned.ALL; entity Deco3a8Reg is port ( D : in std_logic_vector (2 downto 0); CE : in std_logic; Clk : in std_logic; Reset : in std_logic; Q : out std_logic_vector (7 downto 0) ); end Deco3a8Reg; architecture Decodificador of Deco3a8Reg is begin process(D,Reset,Clk) begin case D is when "000" => Q <= "00000001"; when "001" => Q <= "00000010"; when "010" => Q <= "00000100"; when "011" => Q <= "00001000"; when "100" => Q <= "00010000"; when "101" => Q <= "00100000"; when "110" => Q <= "01000000"; when others => Q <= "10000000"; end case; -- Si el reset está activo la salida vale 0 if Reset = '1' then Q <= "00000000"; -- Si hay un flanco de subida del reloj elsif rising_edge (Clk) then -- Si el chip enable está activo if CE = '1' then Q <= D;(Width mismatch. Expected width 8, Actual width is 3 for dimension 1 of D) end if; end if; end process; end Decodificador;
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