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Same Problem (Width mismatches. Expected width to be 8, actual width is 3 for dimension 1 of D

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Experl

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Same Problem(Width mismatch. Expected width 8, Actual width is 3 for dimension 1 of D


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library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_LOGIC_arith.ALL;
use IEEE.std_logic_unsigned.ALL;
 
entity Deco3a8Reg is
    port (
        D : in std_logic_vector (2 downto 0);
        CE : in std_logic;
        Clk : in std_logic;
        Reset : in std_logic;
        Q : out std_logic_vector (7 downto 0)
    );
end Deco3a8Reg;
 
architecture Decodificador of Deco3a8Reg is
 
begin
    
        process(D,Reset,Clk)
        begin
                case D is 
                        when "000" => Q <= "00000001";
                        when "001" => Q <= "00000010";
                        when "010" => Q <= "00000100";
                        when "011" => Q <= "00001000";
                        when "100" => Q <= "00010000";
                        when "101" => Q <= "00100000";
                        when "110" => Q <= "01000000";                  
                        when others => Q <= "10000000";
                end case;
        
                -- Si el reset está activo la salida vale 0
                if Reset = '1' then
                            Q <= "00000000";
                -- Si hay un flanco de subida del reloj
                elsif rising_edge (Clk) then
                    -- Si el chip enable está activo
                    if CE = '1' then
                            Q <= D;(Width mismatch. Expected width 8, Actual width is 3 for dimension 1 of D)
                end if;
        end if;
 
        end process;
 
end Decodificador;

 
Last edited by a moderator:

Re: Same Problem(Width mismatch. Expected width 8, Actual width is 3 for dimension 1

Yes - D is 3 bits, Q is 7 bits. You cannot assign vectors of different widths.
 

Re: Same Problem(Width mismatch. Expected width 8, Actual width is 3 for dimension 1

Yes but how to solve that problem. Should i do a sigAux.
 

Re: Same Problem(Width mismatch. Expected width 8, Actual width is 3 for dimension 1

Solve which problem? Line 40 looks simply wrong.

Output Q is already assigned in combinational part of the process, the assignments in line 35 and 40 will be ignored if the syntax error is solved.

Before fixing the code, you should clarify what you want to achieve.

If the intended function is to register the decoded signal, you can use an auxiliary signal. Or execute the decoder under the clock edge sensitive condition.
 

Re: Same Problem(Width mismatch. Expected width 8, Actual width is 3 for dimension 1

Logic is not making any sense when you write Q<=D, you may concatenate 00000 with the D to solve the error or assign some other value.
 
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    FvM

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