LVS using Cadence Encounter

I am working on a digital design and i synthesized the design using synopsys. My next step is physical design using encounter.

I have done analog layout design using cadence. I could do DRC run and LVS on the same tool. Same as that for digital layout design in Encounter how can i do the DRC and LVS. Can i do it solely with encounter or do i have to do the verification with other tools/procedure. I am learning for an interview so i am willing to learn the basic procedure atleast required for DRC and LVS. I read calibre is also used for DRC, LVS verification purpose. There are many kinds in Calibre. What are the names of the verification tools for Digital design. Can someone plsss help!!! Thank you!!!

This completely depends on your flow but in general when you finish P&R you'll end up with a netlist and a .def file (or a gds, or something else but .def is the least problematic in cadence tools I think). So what you can do is you can import the verilog netlist as a schematic (or just netlist), and you can import .def as a layout view. You can then compare these two using calibre LVS or Assura LVS or whatever LVS (you can compare layout vs layout, netlist vs layout, netlist vs netlist, only your imagination is the limiting factor and also the tool you are using). This is just one way of doing LVS on digital design, I'm sure someone more experienced can guide you more.

To be honest, as long as encounter does not fail catastrophically it usually generates a netlist/layout/def that passes the LVS. Problem usually arises from the connections between the digital and IO ring or other blocks and this requires instantiating the digital block in your schematic and run LVS. If you are sure that encounter did a great job you can actually create a black box model and tell calibre LVS to only check for the pins of this black box. Look at LVS BOX option.

About the DRC, as far as I know (feel free to correct) encounter does not actually run a full scale DRC, it basically checks the lef files which have the geometry of blocks, places them appropriately and checks metal distance rules while trying to route things. If there are issues with the digital cells themselves, there's a chance that encounter may miss them. Also if the lef files are wrong, encounter may place connections to weird parts of digital cells. So when you import the output of encounter as a layout it's usually a good practice to run DRC with whichever tool you have, there doesn't have to be connection information for DRC.

To be honest best way you can learn this is actually doing it. Follow a tutorial or something, synthesize, P&R and connect the outputs of a block to another analog block and run top level LVS DRC for this using whichever tool you have.

But I'm writing these from mixed signal point of view, I'm pretty sure digital oriented people may have much better understanding on the subject.

That is correct, Encounter has a very simplified DRC deck based on the .lef file. For full DRC you need calibre or similar. Cadence offers PVS that is integrated to encounter so you at least get the violation markers inside encounter for easy debugging.