What does this value mean ?

What does this value mean: 6.40690750792007e+71? yy and er1 are real variables.

Hi,

it seems to be 64 bit floating point variables.

its about 6.04 x 10^71

for a binary representation you need about 230 bits :-(
(if my mental math is correct)

Klaus

I would say that you have not initialised these variables so they contain either a random bit sequence or they have been set to some default value by the compiler to indicate that they are not initialised or (possibly more likely as there are two the same) this is the default power-up bit settings of the RAM.
Your variable 'v' is probably similar.
Susan

Aussie Susan said:

I would say that you have not initialised these variables so they contain either a random bit sequence or they have been set to some default value by the compiler to indicate that they are not initialised or (possibly more likely as there are two the same) this is the default power-up bit settings of the RAM.
Your variable 'v' is probably similar.
Susan

Click to expand...

A VHDL or Verilog simulator (Vivado simulator) initializes all variables/signals/reg values to U at simulation start. This is not the same as something like C which will have whatever was left over in memory at the time the variable was allocated until you initialize it.

In this case the values are a VHDL real type with the value either initialized to those values sometime after 0ns or were assigned those values by some assignment statement.

ads-ee said:

A VHDL or Verilog simulator (Vivado simulator) initializes all variables/signals/reg values to U at simulation start. This is not the same as something like C which will have whatever was left over in memory at the time the variable was allocated until you initialize it.

In this case the values are a VHDL real type with the value either initialized to those values sometime after 0ns or were assigned those values by some assignment statement.

Click to expand...

Actually, VHDL only does the 'U' initialization for std_ulogic and types derived from std_ulogic. What the LRM says is to initialize signals and variable to the 'first' value in the type (I'm paraphrasing a bit). The 'U' value in std_ulogic is located in the first position of the definition of the type std_ulogic. Signals/variables that are reals, integers, naturals, user defined types do not get this uninitialized 'U' value, they get a value that depends on the type.

signal SomeReal: real; -- Will initialize to a really big negative real value
signal SomeInteger: integer; -- Will initialize to a really big negative integer value
signal SomeNatural: natural; -- Will initialize to 0
signal SomeNatural: positive; -- Will initialize to 1

type MyType is (Red, Green, Blue);
signal SomeMyType; -- Will initialize to 'Red'

Since the OP posted the value as being 6.40690750792007e+71, that value cannot be the result of an uninitialized signal of type real.

Kevin Jennings

Since the OP posted the value as being 6.40690750792007e+71, that value cannot be the result of an uninitialized signal of type real.

Click to expand...

Agreed. Real variables or signals also don't appear in synthesizable HDL, we can only guess that the code is either part of a test bench or a general HDL "program" not related to hardware logic. It's easy to get large numbers in arbitrary calculations, the number as such exactly "means" it's value. If you want to ask why your code generates such a large number, you are supposed to show it.