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Layout: shared NWELL

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NiedeLu

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Hi experts,
as I'm not very familiar with layout and I intend to do my first one, I have some questions:

For my circuitry I need some matched serial stacked PMOS transistors with the bulk connected to the same node (VDD). During the design phase I used 4 terminal devices of the PDK.

This is how one of this devices looks like (P-cell) -> P-Cell.PNG
(no bulk connection included)

For matching purpose I used a common centroid layout at each stage of the serial stack. I wanted to share the same NWELL with all transistors.

1. If I draw a NWELL over the complete stacked transistor block I get some shorts from diffusion to VDD (NWELL). But not for all diffusions. Please have a look at the attachment -> Stack2.PNG + Stack.PNG.
Can anyone explain why I get this shorts? Or is it just a tool issue?

2. Is the bulk connection done in a right way? I used NTAPS over the whole NWELL.

Kindly asking for your help.

BR
Lukas

Edit: shorts can be seen as yellow crossed rectangulars
 

Attachments

  • P-Cell.PNG
    P-Cell.PNG
    5.4 KB · Views: 92
  • Stack2.PNG
    Stack2.PNG
    45.4 KB · Views: 109
  • Stack.PNG
    Stack.PNG
    241.2 KB · Views: 100

Hello NiedeLu, looking at Stack2, I think so many n-taps are not required. You can create two n-taps at top and bottom, or, left and right. If there is a problem of n-tap distance from a gate, then you can place a n-tap at the middle of the structure or maybe 2 n-taps at 1/3rd distance from left and 2/3rd distance from left.
Covering the whole p-mos array with n-well is ok. You have done the right thing.
Please run LVS and see whether there are any errors.
 
Array.PNG

Hi debdut,
thx for your answer.
As it's a big Array that has to match properly I wanted to make it as symmetric as possible. Therefore I added many NTAPs and a dummy structure around it (red). Area is no issue for this layout. The main task is to ensure that layout has as less impact as possible. It's a very low power circuitry.

Do you have any guess why I get this shorts after I draw the NWELL? In my opinion there can't be a short to the NWELL as the D/S of the PMOS are P+. Am I missing something?

BR
Lukas

Edit: DRC with NWELL is a pass
 

" I used NTAPS over the whole NWELL."

Did you draw a single polygon over the entire NWELL?

Try removing the NTAPS and place one in a one at the wdge of your NWELL. Stretch the well out a little if needed. This may help narrow down your problem.
 

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