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PrimeTime, check_power ,out_of_range table ,out_of_range lamps-loads

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draser

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Hello,

i have done the synthesis of a design and after that i want to measure its power consumption with PrimeTime.

The only warnings i get are : Warning: There are 567 out_of_range ramps.
Warning: There are 106 out_of_range loads.

can i ignore them?i have tested the design in modelsim and it seems to operate fine.

Thank you in advance.
 

draser said:
Hello,

i have done the synthesis of a design and after that i want to measure its power consumption with PrimeTime.

The only warnings i get are : Warning: There are 567 out_of_range ramps.
Warning: There are 106 out_of_range loads.

can i ignore them?i have tested the design in modelsim and it seems to operate fine.

Thank you in advance.
Click to expand...

NO you can't.

Your std cell library has requirements for max transition times at input pins and max load at output pins. you have to tell synthesis about those, so a DRV-free design can be generated.

you have to fix those or the power value calculated is somewhat meaningless.

- - - Updated - - -

there's also a chance that you set no output load for IOs and/or ideal inputs. those would cause out_of_range warnings too.
 
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ThisIsNotSam said:
NO you can't.

Your std cell library has requirements for max transition times at input pins and max load at output pins. you have to tell synthesis about those, so a DRV-free design can be generated.

you have to fix those or the power value calculated is somewhat meaningless.
Click to expand...

So what may generate these warnings?Do you have any advices on what i can do to eliminate them?I searched but i found nothing helpful so far...
The only warnings i found in modelsim were some vital glitches and they did not occur on the input-output ports of my design so i ignored them.


- - - Updated - - -

"there's also a chance that you set no output load for IOs and/or ideal inputs. those would cause out_of_range warnings too."

in order to set output load i use this command "set_load $normal_load [all_outputs]" ?
 

draser said:
So what may generate these warnings?Do you have any advices on what i can do to eliminate them?I searched but i found nothing helpful so far...
The only warnings i found in modelsim were some vital glitches and they did not occur on the input-output ports of my design so i ignored them.


- - - Updated - - -

"there's also a chance that you set no output load for IOs and/or ideal inputs. those would cause out_of_range warnings too."

in order to set output load i use this command "set_load $normal_load [all_outputs]" ?
Click to expand...

- you must tell the synthesis tool what is the maximum transition time. it will then make sure every input of every std cell is respecting that.
- you must thell the synthesis tool what is the maximum cap load. it will then make sure every output of every std cell is respecting that. this rule is pretty similar to a max fanout sort of rule.
- you must set the transition time of the primary inputs of your circuit so they don't look ideal. usually what we do is we tell the synthesis tool what a fictitious driver would look like. ie, tell the tool that the primary input of your circuit behaves as the output of an inverter X1.
- you must set the load on all primary outputs of the circuit. it seems this one you have done, but not the other 3 above.

I don't know which synthesis tool you are using, but the commands used to model the behaviours above are pretty common. should be very easy to find in the documentation. there are SDC commands for setting these parameters too.
 
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Thank you very much,i am going to set all the above constraints and see what happens.

By the way i am using synopsys DC .

About the third point: i am testing my synthesized netlist with a not synthesized design in modelsim so i think that the inputs would be ideal.

About the load:how can i know the load of a design that is not synthesized?Because in my testbench i am connecting the inputs and the outputs of my synthesized netlist with not synthesized designs.
 

about the loads: if these are primary outputs of the circuit, they will be connect to pads. you can use the capacitance of the pad as the output load.
 

Is there any way to measure the power without fixing the out_of_range ramps/loads??
Some violations are inevitables.

for example i have read that in PrimeTime if i use the time-based mode then the power of vital glitches are estimated too.Dont the out_of_range signals have a relation with this power consumed by the vital glitches??

Can i see where these out_of_range signals occur?I mean in what part of my design..Because the PrimeTime just refers that i have XXX amount of these signals.
 

ThisIsNotSam said:
about the loads: if these are primary outputs of the circuit, they will be connect to pads. you can use the capacitance of the pad as the output load.
Click to expand...

How can i do this?i am using library 90nm UMC.How can i know the capacitance of the pad??

Could you explain me a bit more also your point "- you must set the transition time of the primary inputs of your circuit so they don't look ideal. usually what we do is we tell the synthesis tool what a fictitious driver would look like. ie, tell the tool that the primary input of your circuit behaves as the output of an inverter X1." . I understood the rest.

Thank you
 

draser said:
How can i do this?i am using library 90nm UMC.How can i know the capacitance of the pad??

Could you explain me a bit more also your point "- you must set the transition time of the primary inputs of your circuit so they don't look ideal. usually what we do is we tell the synthesis tool what a fictitious driver would look like. ie, tell the tool that the primary input of your circuit behaves as the output of an inverter X1." . I understood the rest.

Thank you
Click to expand...

point #1: do you have a pad library? It is a secondary library, it doesn't come with your standard cells. If you have, the cap values are inside the .lib file of the pad library. you use that value with the set_load command

point #2: If your inputs are ideal, they transition in zero time. this is not realistic, and might cause timing violations. so what you do is you tell your tool that they behave like as if they were coming from the output of a cell. check the command below:
set_driving_cell -lib_cell MY_INV_CELL -library MY_LIB -pin "Y" [get_ports {i_wb_adr[31]}]
what this command does is... it tells the tool that my input named i_wb_adr[31] behaves as the output Y of cell MY_INV from lib MY_LIB
 
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allright , with the option check_power - verbose i could see more informations about the warnings.

They are all like this:

ramp 0.00 at pin 'C1' of cell 'slavefabric/aw_1/u37' is out of ramp range (0.01, 0.78) of lib_cell 'AOI222X1'
load 0.00 at pin 'O' of cell 'slavefabric/aw_1/u38' is out of load range (0.00, 1.20) of lib_cell 'INVX6'

the first must mean that the time transition is zero and the second that the load the cell drives is zero.Does this mean that my tool cannot measure this signal,or does the tool do the power measurement but it warns me that this is not "logic"?
 

ThisIsNotSam said:
point #1: do you have a pad library? It is a secondary library, it doesn't come with your standard cells. If you have, the cap values are inside the .lib file of the pad library. you use that value with the set_load command
Click to expand...



Here is my library file but i cannot understand what the load i should set to my design..Could you please tell me how can i find this?I do not see anything like "pad capacitance = ".
 

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draser said:
about point #1:Here is my library file but i cannot understand what the load i should set to my design..Could you please tell me how can i find this?I do not see anything like "pad capacitance = ".
Click to expand...

I'm afraid you didn't understand my initial point. I asked if you have a pad library. The file you just posted is a standard cell library.
 

ThisIsNotSam said:
I'm afraid you didn't understand my initial point. I asked if you have a pad library. The file you just posted is a standard cell library.
Click to expand...

No,this is my only library..Should i have one?

About point#2: Thanks,now i understood why i must do this.Also by setting the inputs to drive 0.2 pF ,then my out_of_range ramps are reduced to 350.
If my design is using 3 components,should i do this for every of these components , or only to the primary inputs of my design?

- - - Updated - - -

Ramp time is the time a signal need to change its inputs??so if the warn says ramp 0.00 at pin 'C1' of cell 'slavefabric/aw_1/u37' is out of ramp range (0.01, 0.78) of lib_cell 'AOI222X1' it means that the ramp time is zero,and this cannot happen?if so,how can i raise my ramp time?

Please if someone knows..i struggle with this for days..
 

draser said:
No,this is my only library..Should i have one?

About point#2: Thanks,now i understood why i must do this.Also by setting the inputs to drive 0.2 pF ,then my out_of_range ramps are reduced to 350.
If my design is using 3 components,should i do this for every of these components , or only to the primary inputs of my design?

- - - Updated - - -

Ramp time is the time a signal need to change its inputs??so if the warn says ramp 0.00 at pin 'C1' of cell 'slavefabric/aw_1/u37' is out of ramp range (0.01, 0.78) of lib_cell 'AOI222X1' it means that the ramp time is zero,and this cannot happen?if so,how can i raise my ramp time?

Please if someone knows..i struggle with this for days..
Click to expand...

If you don't have pads then you can't really build a chip. It is fine for some early circuit analysis and rough evaluation of power and timing.

about ramp time: when your standard cells were characterised, the vendor had to do so for a range of input slopes (ie ramps that are as fast as 0.01 or as slow as 0.78). 0.0 is not in that range, because it is artificial. to raise your ramp time, you have to model the signal slope.
 
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ThisIsNotSam said:
If you don't have pads then you can't really build a chip. It is fine for some early circuit analysis and rough evaluation of power and timing.

about ramp times: when your standard cells were characterised, the vendor had to do so for a range of input slopes (ie ramps that are as fast as 0.01 or as slow as 0.78). 0.0 is not in that range, because it is artificial. to raise your ramp time, you have to model the signal slope.
Click to expand...

In order to model the signal slope i used the command set_input_transition 0.2 [all_inputs] and the corresponding command for the clock inputs. Despite that i still have some remaining cells inputs that have 0 ramp time.
Some of these inputs are the primary inputs of my design,shouldn't their ramp time raised with the previous command i used?

I think that all of them should be primary inputs of my design, because the ramp time of the rest inputs of the cells of internal design should be set between the acceptable range during synthesis,right?
 

Right. That command should be enough.

For the warnings that you are still seeing it would be necessary to trace back the logic. Maybe there is some other issue somewhere else. Do you have memories in your design?
 
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ThisIsNotSam said:
Right. That command should be enough.

For the warnings that you are still seeing it would be necessary to trace back the logic. Maybe there is some other issue somewhere else. Do you have memories in your design?
Click to expand...

I do not have memories,only registers,clock_network and combinational.The kind of warnings are:

ramp 0.00 at pin 'D' of cell '../adress_out_regx21x' is out of ramp range (0.01, 0.78) of lib_cell 'QDFFRBX1' . This pin D is connected directly with the input port of my main design

ramp 0.00 at pin 'A2' of cell '../u7' is out of ramp range (0.01, 0.78) of lib_cell 'AO222X1' again this pin A2 is connected with the input of my main design.

As i see in my netlist there is no logic between these and my primary inputs.i have these port maps:

port map ( cell_input=> component_input )
port map ( component_input => main_design_input )

I have just almost confirmed that all the warnings are connecting with my primary_inputs by this way.
 

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