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LNA differences between layout ans schematic

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tm.torabi

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Hi,
I have a LNA schematic and layout. The gain (and also other specifications) results of layout simulation are shifted to the left compared to the schematic. It can be seen in the next figure.

LNA Gain.jpg


I changed the routing and placement to decrease this difference, but it does not change. Is there anyway to make this difference fewer?

Thank
 

There may be only so much you can do with placement,
if your parasitic capacitances / inductances are set by
an immovable pad frame of certain pad size and so on.
I'd begin with pushing known / knowable parasitics back
onto the schematic and try for convergence of results
(not simulator solution convergence, but outcome-match).
Once you see what makes the big difference, you can
work the layout more effectively (up to the limits of
rules and available devices, anyway).
 

tm.torabi said:
Hi,
I have a LNA schematic and layout. The gain (and also other specifications) results of layout simulation are shifted to the left compared to the schematic. It can be seen in the next figure.

Thank
Click to expand...
its normal that schematics and layout defers in results/S21.

- - - Updated - - -

tm.torabi said:
I changed the routing and placement to decrease this difference, but it does not change. Is there anyway to make this difference fewer?

Thank
Click to expand...

based on my experience, changing routing alone is not enough because your microstrip line is an inductor itself. all you need to do is re-optimize the circuit lumped component with the layout also. tools like ADS provides better interface between layout and schematics with one more level simulation which called MLIN simulation.
 

Would you please give me a rough estimation of the differences between the peak of Gain in simulation and the layout? And also the differences I showed in the above figure?
Actually, I have about 5DB difference between the peak of Gain and I didn't find anyway to decrease this. The same problem with the gap I talk about before.

Thanks for your replies
 
Last edited:

hi,
its really hard to estimate the difference you will see between layout and circuit simulations! its really depends on the complexity of a layout. there is no equation to predict that!

5dB looks normal to me. your statement saying you didnt find any way to decrease it sounds weird to me! are you using lumped component in your design? if yes, all you need to do is optimize them and again to get same results a circuit in schematic. you may end up in different component values for layout and schematics. its normal and remember that its as a results of cancelling parasitics caused layout.
 
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    posiba

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pragash said:
hi,
its really hard to estimate the difference you will see between layout and circuit simulations! its really depends on the complexity of a layout. there is no equation to predict that!

5dB looks normal to me. your statement saying you didnt find any way to decrease it sounds weird to me! are you using lumped component in your design? if yes, all you need to do is optimize them and again to get same results a circuit in schematic. you may end up in different component values for layout and schematics. its normal and remember that its as a results of cancelling parasitics caused layout.
Click to expand...

Thanks pragash
I am beginner and I always thought the schematic and layout should have the same device sizes, otherwise I know it's not that much hard to get a good results.
 

hi torabi,
welcome to real world (layout). real world (layout) can never be the same as theory (schematics) because of parasitic of layout. :grin:
 

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