Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Delayed assign in Verilog

Status
Not open for further replies.
S

shaiko

Advanced Member level 5
Joined
Aug 20, 2011
Messages
2,644
Helped
303
Reputation
608
Reaction score
297
Trophy points
1,363
Activity points
18,302
Hello,

1. Is the following legal in Verilog?
Code: 
assign #5 a = ~a;
2. Will it have the same effect as the following VHDL code?
Code: 
a <= not a after 5ns ;
3. Is it possible in Verilog to explicitly set the time delay units in code? (such as with the 5ns example in VHDL).
 

1. It is legal. (You wait for 5 time units, invert value of a and assign it to a)
2. This is different. you are modelling transport delay here.
3.Define the timescale accordingly..
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
With VHDL, this will generate a periodic waveform:
Code: 
a <= not a after 5ns ;

Why should this yield a different result?
Code: 
assign #5 a = ~a;

We assign the inverted value of a to itself with a delay of 5 - and we do it all the time. It sounds like this block of code should also yield a periodic waveform with a duty cycle of 50%.
 

I agree with you. The result should be the same if your intention is to generate clocks.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
As far as I know, assign just models combinational logic, but the code above has a time-dependent command, which also could not synthesize.
 

As far as I know, assign just models combinational logic, but the code above has a time-dependent command, which also could not synthesize.
Click to expand...
Of course. My question is about simulation.
 

Uh, assign #5 a = ~a; isn't going to work in simulation. All you'll get is x as a cannot be initialized as it is defined as a wire and you can't initialize a continuous assignment.

So you won't be able to generate a clock in this fashion.

Use one of these to generate a clock in the testbench in Verilog:
Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

// define a as a reg
reg a;
 
// using forever
initial begin
  a = 0;
  forever #5 a = ~a;
end
 
// using always
initial begin
  a = 0;
end
always begin
  #5 a = ~a;
end
 
// alternative using always (starts off as x unless you add an initial block)
always begin
  #5 a = 0;
  #5 a = 1;
end
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
ads-ee said:
Uh, assign #5 a = ~a; isn't going to work in simulation. All you'll get is x as a cannot be initialized as it is defined as a wire and you can't initialize a continuous assignment.
Click to expand...
This will work in SystemVerilog if a is defined as a bit.

Code: 
bit a;
assign #5ns a = ~a;
 
Last edited:
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
This will work in SystemVerilog if a is defined as a bit.
Click to expand...
Is bit a standard type?
Is it synthesizable with SV ?
 

dave_59 said:
This will work in SystemVerilog if a is defined as a bit.

Code: 
bit a;
assign #5ns a = ~a;
Click to expand...

Just tested this in both Modelsim and Vivado's simulator. Works fine in Modelsim, but doesn't work correctly in Vivado's simulator (a changes one time from 0 to 1 and never updates after that.

Unfortunately we only have a couple of Modelsim licenses and they get hogged by others so I have to use Vivado's simulator and unfortunately it's SV support is spotty at best and isn't even officially documented.

I used the following code to test this.
Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13

`timescale 1ns/1ns
 
module assign_test;
 
  bit a;
 
  assign #5 a = ~a;
 
  initial begin
    $monitor ("%t - a = %b", $time, a);
  end
 
endmodule


Vivado output:
Code: 
Time resolution is 1 ns
xsim% run 100  ns
                   0 - a = 0
                   5 - a = 1

modelsim output:
Code: 
Time resolution is 1 ns
xsim% run 50
                   0 - a = 0
                  10 - a = 1
                  15 - a = 0
                  20 - a = 1
                  25 - a = 0
                  30 - a = 1
                  35 - a = 0
                  40 - a = 1
                  45 - a = 0
                  50 - a = 1

- - - Updated - - -

Bit is a standard SV type, and will synthesize.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top