T
treez
Guest
Hello,
We wish to make a 230VAC input dual, interleaved Boost PFC stage (3.5kW) whose output voltage can be tightly controlled from 330VDC to 440VDC.
Dual PFC controller chips like FAN9672 simply don’t allow this wide range of output voltage control. Therefore we need to make our own PFC controller with a microcontroller running code that we write.
In order to have good duty cycle resolution we would need the microcontroller to be running at a very high frequency. However, above 1kw in power level, the PFC regulations on mains harmonics get slacker and so a “Modified” PFC algorithm can suffice…as follows. We simply switch the Boost FET at just a couple of different duty cycles…if on maximum power, then we switch the FET right across the mains half cycle. As the power reduces, we simply have an interval of time near the zero crossing where the FET is not switched at all….and we increase this “dead-time” interval as the power throughput is required to reduce further.
Do you believe this is an acceptable PFC algorithm for this power level?
(its just that we must do this quickly and with minimal code complexity for our junior software engineer)
We wish to make a 230VAC input dual, interleaved Boost PFC stage (3.5kW) whose output voltage can be tightly controlled from 330VDC to 440VDC.
Dual PFC controller chips like FAN9672 simply don’t allow this wide range of output voltage control. Therefore we need to make our own PFC controller with a microcontroller running code that we write.
In order to have good duty cycle resolution we would need the microcontroller to be running at a very high frequency. However, above 1kw in power level, the PFC regulations on mains harmonics get slacker and so a “Modified” PFC algorithm can suffice…as follows. We simply switch the Boost FET at just a couple of different duty cycles…if on maximum power, then we switch the FET right across the mains half cycle. As the power reduces, we simply have an interval of time near the zero crossing where the FET is not switched at all….and we increase this “dead-time” interval as the power throughput is required to reduce further.
Do you believe this is an acceptable PFC algorithm for this power level?
(its just that we must do this quickly and with minimal code complexity for our junior software engineer)