Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

what will affact ACLR? please discussing

Status
Not open for further replies.
ACLR (Adjacent Channel Leakage Ratio) is a very important specification in WCDMA systems for the transmitter, especially the power amplifier. It is defined as the ratio of the power in the adjacent channel to the power in the user (wanted) channel,

ACLR = 10 log (PADJACENT/PWANTED) [dBc]

effect occurs with broadband signals and is by the odd terms (IM3, IM5, etc) of the transfer function of building block.
The first adjacent channel distortion (ACLR1-adjacent) result from both the 3rd order and the 5th order distortion mechanisms, whereas the second adjacent channel (ACLR2-alternate) is dominated by the 5th order distortion mechanisms. The overall distortion at IM3 frequency (ACLR1) is a vector sum of the distortions generated by the third and fifth order nonlinearity.
The linearity of the transmitter chain is the main contributor keeping good ACLR.
 

ACLR (Adjacent Channel Leakage Ratio) is a very important specification in WCDMA systems for the transmitter, especially the power amplifier. It is defined as the ratio of the power in the adjacent channel to the power in the user (wanted) channel,

ACLR = 10 log (PADJACENT/PWANTED) [dBc]

effect occurs with broadband signals and is by the odd terms (IM3, IM5, etc) of the transfer function of building block.
The first adjacent channel distortion (ACLR1-adjacent) result from both the 3rd order and the 5th order distortion mechanisms, whereas the second adjacent channel (ACLR2-alternate) is dominated by the 5th order distortion mechanisms. The overall distortion at IM3 frequency (ACLR1) is a vector sum of the distortions generated by the third and fifth order nonlinearity.
The linearity of the transmitter chain is the main contributor keeping good ACLR.






1. Reduce your PA input power, or select a PA with high linearity.

In terms of PA, if your output power is too large, the PA will saturate.

image001.gif

Intermodulation (IMD) is one of nonlinearities due to saturation.

image003.png


As vfone said, at saturation, there will be IMD3 and IMD5, which degrade ACLR.

image005.png


It’s the reason why poor ACLR usually occurs in maximum power.
Thus, ACLR is the linearity indication of your Tx chain.
If you reduce your PA input power, or select a PA with high linearity, then ACLR improves.






2. Optimize your load-pull

image007.png


Generally speaking, for convenience,
we usually tune the load-pull to around 50 Ohm on Smith Chart.
But if you really wanna optimize your ACLR,
you can tune the load-pull to the location with best ACLR on Smith Chart.
Of course, good linearity is at the expense of efficiency,
it means that your current consumption will increase.
After all, it’s a trade-off between linearity and efficiency.



3. Decrease your PA post-loss

Take WCDMA for example, the block diagram is as below :

image009.png


Of course, both antenna switch module(ASM) and duplexer have insertion loss.
We call the total insertion loss at PA output “PA post-loss”,
and the relationship between PA output power and post-loss is illustrated as below :

image012.jpg




For example, if you hope the measured Tx power at antenna(Target power) is 24 dBm,
and your PA post-loss is 3dB, it means that your PA output power is 27 dBm.
Likewise, with the same target power, if your PA post-loss is 5dB, your PA output power is 29 dBm.
Thus, according to the above formula, we know that more the PA post-loss, more PA output power.

image014.jpg


As mentioned above, more PA output power leads to worse linearity, which degrades ACLR.






4. Fine tune your PA input matching :

image015.png


As illustrated above, PA input matching is the driver amplifier (DA) load-pull.
That is to say, if your DA load-pull is not good enough for linearity, then the ACLR at PA input will become poor.
And PA is the biggest contributor to nonlinearity, poor ACLR at PA input leads to worse ACLR at PA output.

image017.png


As a thumb of rule, the ACLR at PA input should be lower than which at PA output about 10 dB.
For example, if you hope you have -40 dBc ACLR at PA output, then the ACLR at PA input should be -50 dBc.


Because DA output power is lower than PA output power,
t proves that ACLR is related to output power again.

image019.png







5. Put SAW filter at PA input

As mentioned above, IMD degrades ACLR.
And the IMD near RF signal may be composed of RF signal itself and harmonics.

image021.png


2F – F = F
3F-2F = F

Thus, if we put SAW filter at the PA input to reject these harmonics,
and then IMD decreases, ACLR improves.
Based on the analysis, BAW is better than SAW

image023.png

And FBAR is better than BAW :

image025.jpg


Nevertheless, the insertion loss of SAW filter at PA input is also the DA post-loss.
And DA output power has to be strong enough to boost PA.
That is to say, higher the insertion loss of SAW filter at PA input,
higher DA output power, and higher ACLR at PA input.
As mentioned above, higher ACLR at PA input leads to much higher ACLR at PA output.



6. Avoid IR drop in Vcc of PA

As illustrated as below, lower Vcc, worse ACLR :

image026.png


Generally speaking, in Vcc, there are series bead or inductor acting as RF choke.
Thus, if the internal resistance within them is too large, which causes IR drop , and degrades ACLR.

Besides, if the layout trace of Vcc is too thin or long, there will be IR drop as well.

Of course, if the above situations occur in Vcc of transceiver,
then ACLR at PA input degrades.
And poor ACLR at PA input leads to worse ACLR at PA output.




7. Digital pre-distortion (DPD)

As illustrated below :

image028.png


After DPD, the ACLR improves much due to PA linearity improvement.

image030.png





8. Reject DC-DC converter Switching Noise

As illustrated below :

image032.png


DC-DC converter Switching Noise and RF signal may compose IMD2, which is near RF signal :

image034.png


That is to say, less the switching noise, less the IMD2 and ACLR.




Thus, we can reject switching noise by means of bead or inductor. As illustrated below :

image036.gif


There are 6 cases :

image038.png


image040.gif





Let’s assume switching noise is 6 MHz.
As shown above, comparing with case1(original condition),
we can see that the insertion loss at 6 MHz becomes more in other cases,
it means that inserting inductor or bead between DC-DC converter and Vcc of PA really rejects switching noise. Because the insertion loss of case 3 is largest, the ACLR of case 3 improves most.

image042.gif

Of course, as mentioned above, the internal resistance within the inductor and bead should not be too large,
or there will be IR drop and ACLR degradation.



9. Delay of Envelope Tracking (ET)

ET requires an additional generator to provide the envelope signal for the DC modulator.
Envelope signals demand highly precise adjustable time alignment with the RF signal,
shaping capabilities and a signal performance with best spectral purity.

image044.jpg

Therefore, highly precise synchronization is the key, which impacts ACLR very much.

image046.png


As illustrated above, there is an optimum time delay for ACLR.
Thus, you can adjust time alignment to achieve best ACLR




In conclusion, for ACLR, there 9 points you should pay attention to :

1. PA output power and linearity
2. PA load-pull
3. PA post loss
4. PA input matching
5. SAW filter at PA input
6. Vcc IR drop
7. DPD
8. DC-DC converter switching noise
9. Time delay between envelope signal path and RF signal path
 
Now I found that this forum has no limitations in how many pictures you can place in one post.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top