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RC-extractions/coners -> how many should be done for SignOff

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ivlsi

ivlsi

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Hi All,

How many RC-extraction checks should be done for STA SignOff? Let's consider 40nm and 28nm processes.

Thank you!
 

The foundry recommends Cworst/RCworst/Cbest/RCbest with three different temps (-40, 25, 125).
 
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Re: RC-extractions/coners -> how many should be done for SignOff

oratie said:
The foundry recommends Cworst/RCworst/Cbest/RCbest with three different temps (-40, 25, 125).
Click to expand...

So, will 4*3=12 corners?

While extracting C-worst corner, what 'R' should be considered?

Is RC extraction done for each net? Why R and C vary? Each net has a final R and C, why a variation of them should be considered?

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Why there is no R-best/worst corner?
 
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During chip manufacturing, the following parameters affect nets RC. Metal width = W, Metal thickness = T, IMD (dielectric) thickness. From wafer to wafer, from chip to chip, even from net to net (on the same chip) all of these parameters can be vary.

The different ratio of these parameters variations will lead to different RC corners:

Cworst = W(max) + T(max) + D(min)
Cbest = W(min) + T(min) + D(max)
RCworst = W(min) + T(min) + W(min)
RCbest = W(max) + T(max) + D(max)

So, answer yourself, which set of parameters will be in Rbest? ;)
 
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Rbest = W(max) + T(max) + D(max), isn't it?
and Rworst = W(min) + T(min) + D(min)

If I am correct, RCbest and RCworst will become same as Rbest and Rworst!!
 

You are right. By the way, thickness of inter-layer dielectric will not affect R of the net.
 
Re: RC-extractions/coners -> how many should be done for SignOff

Oh...that's right. One more question. Is it compulsory that the RCworst corner should be for W(min) + T(min) + D(min) ?? Suppose, in my design, the capacitance effect is so high compared to resistance of the net. In such a situation, won't it be W(max)+T(max)+D(min)??
Still I won't be having a separate Rbest or Rworst corncer since RCworst will become Rbest now.

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oh..sorry for that question. Then my Cworst, RCworst and Rbest corners corners will become same!!
 

in 130nm probably less number of corners will do but these are too simplistic equations you are putting. In lower technologies things become too complicated. Cworst ,Rcworst and Rbest don't become the same ever as you will see violations in each of them. The number of IP corners become very high in mobile SOC because of multiple voltage designs. You should try a big design to run these test cases with various extraction to get the appropriate list. But there is always an increase in the number of corners rather than reduction as you go into lower technologies. It is very expensive to generate these libraries.... but that is the nature of problem ;-)
 

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