VHDL code for implementing NCO

Sherif Welsen · Feb 3, 2005

Hi every body,

Could anybody provide me with a VHDL code implementing the Numerically Controlled Osc. NCO "DDS".

Added after 2 minutes:

Could you provide me with a resources describing the NCO, typical example using LUT or any other method that could be implemented on FPGAs.

nand_gates · Feb 3, 2005

sin vhdl

Hi,
Here is one example of Qadrature oscillator I build and testted on FPGA.
Its a sine wave oscillator.
I posted this code here some time back also it was in verilog.

Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sine_cos is
  
  port (
    clk   : in  std_logic;
    reset : in  std_logic;
    en    : in  std_logic;
    sine  : buffer std_logic_vector(7 downto 0);
    cos   : buffer std_logic_vector(7 downto 0));

end sine_cos;
architecture behave_sine_cos of sine_cos is
signal sine_r, cos_r : std_logic_vector(7 downto 0);
begin  -- behave_sine_cos
 sine <= sine_r + (cos_r(7) & cos_r(7) & cos_r(7) & cos_r(7 downto 3));
 cos  <= cos_r - (sine(7) & sine(7) & sine(7) & sine(7 downto 3));
   
registers: process (clk, reset)
begin  -- process registers
  if reset = '0' then                   -- asynchronous reset (active low)
    sine_r <= "00000000";    
    cos_r <= "01111000";
  elsif clk'event and clk = '1' then    -- rising clock edge
    if (en = '1') then
      sine_r <= sine;
      cos_r <= cos;      
    end if;
  end if;
end process registers;
end behave_sine_cos;

-------------------------------------------------------------------------------
-- Testbench
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity sine_cos_tb is
  
end sine_cos_tb;
architecture behave of sine_cos_tb is
component sine_cos
  port (
    clk   : in  std_logic;
    reset : in  std_logic;
    en    : in  std_logic;
    sine  : buffer std_logic_vector(7 downto 0);
    cos   : buffer std_logic_vector(7 downto 0));
end component;
signal    clk   : std_logic := '0';
signal    reset : std_logic := '0';
signal    en    : std_logic := '1';
signal    sine  : std_logic_vector(7 downto 0);
signal    cos   : std_logic_vector(7 downto 0);

begin  -- behave
clk <= transport not clk after 5 ns;

u1 : sine_cos
      port map (
        clk   , 
        reset , 
        en    , 
        sine  , 
        cos    );
process
  begin  -- process
    wait for 50 ns;
    reset <= '1';
    wait for 10000 ns;
    wait;
  end process;  

end behave;

Hope this helps

Renjith · Feb 3, 2005

nco architecture

Hi Sherif,
An NCO design has got just 2 major blocks.
Phase accumulator, LUT Rom( to store the phase angles of sine and cos).
I've attached a NCO design document, this gives a detailed explanation for the blocks i mentioned above.
Hope this helps

Black Jack · Feb 3, 2005

vhdl nco design

Thank for example.
But I can`t understand how sin and cos obtained.
CORDIC or other methods?
Could you share with this information (app. notes, data sheet, books)

Best Regards,
Victor

nand_gates · Feb 3, 2005

an nco design has got just 2 major blocks.

Hi,

Sine and cos waves are generated using Quadrature oscillator.
If you integrate sine wave you get cosine wave You integrate this cosine
wave to generate input sine wave...
This is done using digital filter techniqe here in the VHDL code...
Following figure will explain it well....

Code:

         +----+      +----+
   sine  | /  | -cos | /  |
    +--->| |  |----->| |  |---+
    |    | /  |      | /  |   |
    |    +----+      +----+   |
    |                         |
    +-------------------------+

Sherif Welsen · Feb 3, 2005

vhdl code for nco

Please colleagues, I want to collect every single detail about the Direct Digital Synthesizer (NCO). Please send every information you have.

Thanks inadvance, I remain.

Black Jack · Feb 3, 2005

vhdl nco example

Sherif Welsen said:
Please colleagues, I want to collect every single detail about the Direct Digital Synthesizer (NCO). Please send every information you have.

Thanks inadvance, I remain.

See www.analog.com for their DDS chips datasheet, app. notes, tutorials.

I think for DDS important 2 things
1) Architectures of Accumulators
2) SIN generation methods (table and table compression, CORDIC, series)

See this link
http://www.sss-mag.com/dds.html

I have this book "Direct Digital Frequency Synthesizers"
by Venceslav F. Kroupa and advice that you read this.

Sherif Welsen · Feb 3, 2005

cosine vhdl

Black Jack said:
I have this book "Direct Digital Frequency Synthesizers"
by Venceslav F. Kroupa and advice that you read this.

How could I get a copy of that book?

Black Jack · Feb 8, 2005

cosine series vhdl code

Sherif Welsen said:
Black Jack said:

I have this book "Direct Digital Frequency Synthesizers"
by Venceslav F. Kroupa and advice that you read this.

Click to expand...

How could I get a copy of that book?

I have only printed version

jony · Feb 21, 2005

vhdl sin

first of all i realy liked your code
but i didn't few thing
1.how did you couculate the phase diffrance at the begining?
2.how did you know to to subscart this spacific vector?

TRUNGDPHAN · May 30, 2005

vhdl codes for nco

I need a detail diagram of NCO architecture. Anyone got it? If yes, please share it for me? Thanks a lot.

ddt694 · May 31, 2005

nco filter tutorial

nco is in fact a accumulator and a lookup table

you can realize a accumulator like this

process(clk) begin
if rising_edge(clk) then
acc(23 downto 0) <= acc(23 downto 0) + input;
end if; end process;

then, you can address the lookup table like this

process(clk) begin
if rising_edge(clk) then
nco_out(7 downto 0) <= rom(conv_integer(acc(23 downto 14));
end if; end process;

the signal "rom" is a lookup table, a sine or cosine waveform is in it. you can generate a sine waveform by using matlab:

step = 1/1024;
t=0: step : 1-step;
sine = sin(2*pi * t);

jishnukkd · Feb 20, 2007

sine_cos

go to codesearch.google.com and search for the codes. I have got the codes fot NCO accumulator, LUT from there.You can select the code language from the Advanced search optin

nardo520 · Apr 16, 2007

nco sine

I need the method of using CORDIC THEORY,who can help me?THANKS...

Added after 11 minutes:

HELP....

echo47 · Apr 17, 2007

ncodesign

nardo520, here is some info on CORDIC:
**broken link removed**

arvindkts · Jan 4, 2010

Re: nco architecture

Renjith said:
Hi Sherif,
An NCO design has got just 2 major blocks.
Phase accumulator, LUT Rom( to store the phase angles of sine and cos).
I've attached a NCO design document, this gives a detailed explanation for the blocks i mentioned above.
Hope this helps

please send me flowchart of your nco code.
i m getting difficulty in understanding it.
I will be thankfull to you for this kind.[/youtube]\][/url][/code]

Dose · Jan 18, 2010

Re: VHDL for NCO

Cordic has no LUT. The value is calculated with shifts and adds.

You can see some cordic examples at

http://www.dossmatik.de/vhdl.html

bijayamuni · May 23, 2011

Re: sin vhdl

nand_gates said:

Hi,
Here is one example of Qadrature oscillator I build and testted on FPGA.
Its a sine wave oscillator.
I posted this code here some time back also it was in verilog.

Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sine_cos is
  
  port (
    clk   : in  std_logic;
    reset : in  std_logic;
    en    : in  std_logic;
    sine  : buffer std_logic_vector(7 downto 0);
    cos   : buffer std_logic_vector(7 downto 0));

end sine_cos;
architecture behave_sine_cos of sine_cos is
signal sine_r, cos_r : std_logic_vector(7 downto 0);
begin  -- behave_sine_cos
 sine <= sine_r + (cos_r(7) & cos_r(7) & cos_r(7) & cos_r(7 downto 3));
 cos  <= cos_r - (sine(7) & sine(7) & sine(7) & sine(7 downto 3));
   
registers: process (clk, reset)
begin  -- process registers
  if reset = '0' then                   -- asynchronous reset (active low)
    sine_r <= "00000000";    
    cos_r <= "01111000";
  elsif clk'event and clk = '1' then    -- rising clock edge
    if (en = '1') then
      sine_r <= sine;
      cos_r <= cos;      
    end if;
  end if;
end process registers;
end behave_sine_cos;

-------------------------------------------------------------------------------
-- Testbench
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity sine_cos_tb is
  
end sine_cos_tb;
architecture behave of sine_cos_tb is
component sine_cos
  port (
    clk   : in  std_logic;
    reset : in  std_logic;
    en    : in  std_logic;
    sine  : buffer std_logic_vector(7 downto 0);
    cos   : buffer std_logic_vector(7 downto 0));
end component;
signal    clk   : std_logic := '0';
signal    reset : std_logic := '0';
signal    en    : std_logic := '1';
signal    sine  : std_logic_vector(7 downto 0);
signal    cos   : std_logic_vector(7 downto 0);

begin  -- behave
clk <= transport not clk after 5 ns;

u1 : sine_cos
      port map (
        clk   , 
        reset , 
        en    , 
        sine  , 
        cos    );
process
  begin  -- process
    wait for 50 ns;
    reset <= '1';
    wait for 10000 ns;
    wait;
  end process;  

end behave;

Hope this helps

Hi I am Bijaya
I want to see the verilog design can you post it please
thanks
Bijaya

VINU BASIL · Nov 22, 2013

Re: an nco design has got just 2 major blocks.

nand_gates said:
Hi,

Sine and cos waves are generated using Quadrature oscillator.
If you integrate sine wave you get cosine wave You integrate this cosine
wave to generate input sine wave...
This is done using digital filter techniqe here in the VHDL code...
Following figure will explain it well....

Code:

+----+ +----+ sine | / | -cos | / | +--->| | |----->| | |---+ | | / | | / | | | +----+ +----+ | | | +-------------------------+

Hello Sir, thanks for the code. I successfully simulated it. It would be very kind of you, if you could explain briefly about the filtering/integration technique that you used.

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