Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

concatenation operator in case statement

Status
Not open for further replies.
R

rameshrai

Full Member level 3
Joined
Aug 16, 2010
Messages
158
Helped
7
Reputation
14
Reaction score
7
Trophy points
1,298
Activity points
2,272
hi,

can i use the following in case statement?

with s1 & s0 select

where s1 and s0 are std_logic

I get error with this:

Select expression must be of a locally static subtype. Use -relax to allow expressions of a nonstatic subtype.

thanks for help
 

Yes,
you can do something like this:
Code: 
process(b0,b1,b2,b3)
   variable bcat : std_logic_vector(0 to 3);
begin
   bcat := b0 & b1 & b2 & b3;
   case bcat is
      when "0000" => x <= 1;
      when others => x <= 2;
   end case;
end process;

I got the example from some site
 
In VHDL 2008, this rule is relaxed, so concatenations are allowed.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top