Ram Problem, help me !!!!!!!!!

-- LPM_RAM_DQ
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity LPM_RAM_DQ is
	generic (
		Note: note := "RAM with Separate Input and Output Ports";
		LPM_WIDTH: integer := 16;
		LPM_TYPE: string := "LPM_RAM_DQ";
		LPM_WIDTHAD: integer := 9;
		LPM_NUMWORDS: string := "UNUSED";
		LPM_FILE: string := "UNUSED";
		LPM_INDATA: string := "REGISTERED";
		LPM_ADDRESS_CONTROL: string := "REGISTERED";
		LPM_OUTDATA: string := "UNREGISTERED";
		LPM_HINT: string := "UNUSED" 
	);
	port (
		DATA: in STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0);
		ADDRESS: in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
		WE: in STD_LOGIC;-- := '1';
		INCLOCK: in STD_LOGIC;-- := '0';
		Q: out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0)
	);
	type ENUM_LPM_INDATA is (REGISTERED, UNREGISTERED);
	type ENUM_LPM_ADDRESS_CONTROL is (REGISTERED, UNREGISTERED);
	type ENUM_LPM_OUTDATA is (REGISTERED, UNREGISTERED);
end LPM_RAM_DQ;

architecture LPM_RAM_DQ_arch of LPM_RAM_DQ is
begin
	-- Enter concurrent statements here
end LPM_RAM_DQ_arch;

-- LPM_RAM_DQ: Predefined module ended here



-- DataRam
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity DataRam is
	port (
		data : in STD_LOGIC_VECTOR(15 downto 0);
		addr : in STD_LOGIC_VECTOR(8 downto 0);
		CLK : in STD_LOGIC;
		write : in STD_LOGIC;
		Q : out STD_LOGIC_VECTOR(15 downto 0)
	);
end DataRam;

architecture DataRam_arch of DataRam is

	signal high, low, lpm_write, nclk : STD_LOGIC;

	component LPM_RAM_DQ
	generic (
		LPM_WIDTH: integer := 16;
		LPM_TYPE: string := "LPM_RAM_DQ";
		LPM_WIDTHAD: integer := 9;
		LPM_NUMWORDS: string := "UNUSED";
		LPM_FILE: string := "UNUSED";
		LPM_INDATA: string := "REGISTERED";
		LPM_ADDRESS_CONTROL: string := "REGISTERED";
		LPM_OUTDATA: string := "UNREGISTERED";
		LPM_HINT: string := "UNUSED" 
	);
	port (
		DATA: in STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0);
		ADDRESS: in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
		WE: in STD_LOGIC;-- := '1';
		INCLOCK: in STD_LOGIC;-- := '0';
		Q: out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0)
	);
	end component;

begin
		high<='1'; low<='0';
		lpm_write <= write and clk;
		nclk <= not clk;
		U_LPM_RAM_DQ: LPM_RAM_DQ port map(data, addr, write, clk, Q);
		
		
		 		
end DataRam_arch;

module RAM (
	address,
	we,
	clock,
	data,
	q);

	input	[7:0]  address;
	input	we;
	input	clock;
	input	[7:0]  data;
	output	[7:0]  q;

	wire [7:0] sub_wire0;
	wire [7:0] q = sub_wire0[7:0];

	lpm_ram_dq	lpm_ram_dq_component (
				.address (address),
				.inclock (clock),
				.data (data),
				.we (we),
				.q (sub_wire0));
	defparam
		lpm_ram_dq_component.intended_device_family = "FLEX10K",
		lpm_ram_dq_component.lpm_width = 8,
		lpm_ram_dq_component.lpm_widthad = 8,
		lpm_ram_dq_component.lpm_indata = "REGISTERED",
		lpm_ram_dq_component.lpm_address_control = "REGISTERED",
		lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
		lpm_ram_dq_component.use_eab = "ON",
		lpm_ram_dq_component.lpm_hint = "MAXIMUM_DEPTH=256",
		lpm_ram_dq_component.lpm_type = "LPM_RAM_DQ",
		lpm_ram_dq_component.lpm_file = "nabilcpu.mif";


endmodule