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Writing testbench in verilog or e language?

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wilfwolf

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I am planning to write a PCMCIA interface testbench. There are two languages I can select, verilog or e, how do I make a decision? Are there any person used both of them before and give me any advices?
Thx.
 

I think use verification language to build testbench will be better.But verilog will be faster when running simulation.
 

I think you should write testbench with E .
 

you have to use e- language.
 

Verilog is the most portable, it is very fast.
 

U have to use e language
 

I have used the jeda, Maybe the e language is good for u.
 

Verilog is the best!
At the most you can try SystemVerilog
Dont ever think of using TestBuilder!!!

e Vera are good but costly!
Vera will be slower because it uses PLI's to integrate with Verilog!
 

forget e. its almost dead. not many use this language anymore. too diffiult to learn and lacks many features of a better environment such as VERA. synopsys gives vera away free if you buy VCS simulator. The language of VERA is C++ so whatever test code you develop will be portable to other tools easier. If you can not afford vera then i suggest verilog. i would use even verilog rather than e/specman.
 

i think verilog is more common,it runs better in simulation
 

E language and Vera, which is better?
 

nand_gates:
why not testbuilder? can you give us more details?
 

Hi wilfwolf,

The answer dependes on how much money you can spend and how big is your design. If you are verifying a multi-million gates ASIC the best choices today are E or Vera (In 2 years from now it will probably be SystemVerilog).
But from your e-mail it seems to me you are doing block level verification. If that is the case verilog may still be a good/reasonable choice.

You may also want to consider SystemC which is gaining a lot of momentum specially in System level verification.

a few comments about previous e-mails:
- It is true that Vera resemmbles C++ but Vera is not C++ and it can not be portable to other tools. Vera is only supported by Synopsis.
- Vera is not free. What is free is VeraLight which is a subset of Vera and don'support the most advanced/poerfull features available in Vera. Vera is a competitor for E (in terms of completeness and power of the language) but VeraLight is not. For small projects VeraLight may be able to use VeraLight but for large ASICs you will need Vera or E.

I hope this helps.

Take care
 

I don't like testbench write use c++ ,becasue verilog
wire or reg have four variable,but c and c++ use 2 variable. when I use c or c++ to write testbench, i feel it have something i don't fell good.
 

I consider that write testbench in verilog. It is is more best than the other language. It will make design flow more easy.
 

to do verification, only verilog can't do very well.
because it need so many vectors to cover the design.
E can provide random test vectors, so using E will be a good choice.
systemverilog is not supported well now, and some temporal is not as well as e.
 

Presenlty e-language has an edge over the other Veriifcation languages.
 

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    wilfwolf

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Verilog is popular , but e is specially designed for verification .
Verilog has good supporting.
 

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