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add and subtract and multiply 4 bits "help"

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crazy-igzp

crazy-igzp

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Hi I’m a beginner in VHDL! I have a problem in simple prog that add and subtract and multiply 4bits
Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity add_sust is
port( E1 : in std_logic_vector(3 downto 0);
      E2 : in std_logic_vector(3 downto 0);
      a  : in std_logic_vector(1 downto 0);
      s  : out std_logic_vector(7 downto 0));
end add_sust;
architecture aaddsust of add_sust is
begin
 process(a,E1,E2)
   
  begin
   if(a="01") then 
        s<=E1+E2;
      elsif(a="10") then 
        s<=E1-E2;
      elsif(a="11") then 
        s<=E1*E2;
   end if;
end process;
end aaddsust;


expression has 4 elements, but must have 8 element !
how can I use the same output ,
 
Last edited by a moderator:

First of all, you should probably make your parameters SIGNED or UNSIGNED, as appropriate to what you're doing.

I'm not sure I understand your question. Your two multiplier inputs are 4 bits, and your product is 8 bits, which is just fine. You might have trouble synthesizing this, but as it is it should simulate ok.
 
the problem it doesn't simulate ! cause the Error message shows up ! " expression has 4 elements, but must have 8 element "
 

What is your simulator?

Regardless, you can just create intermediate 8-bit values by concatenating 4 leading zeroes to your 4-bit values (assuming unsigned numbers-otherwise, you'll have to do sign-extension)
 
I use Quartus II 7.2 ! and ! I didn't understand u ! cause I'm new a little bit in vhdl ! how can I concatenat 4 leading zeroes to my 4-bit !
 

signal e1: unsigned (3 downto 0);
signal x: unsigned(7 downto 0);

x<="0000" & e1;
 
Re: add and subtract and multiply 4 bits &quot;help&quot;

how can I make them signed , with details if possible !
my description


Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity add_sust is
port( E1 : in std_logic_vector(3 downto 0);
      E2 : in std_logic_vector(3 downto 0);
      a  : in std_logic_vector(1 downto 0);
      s1  : out std_logic_vector(7 downto 0));
end add_sust;
architecture aaddsust of add_sust is

begin
 process(a,E1,E2)
   
  begin
   if(a="01") then 
        s1<= "0000" & E1+E2;
      elsif(a="10") then 
        s1<="0000" & E1-E2;
      elsif(a="11") then 
        s1<=E1*E2;
   end if;
end process;
end aaddsust;

- - - Updated - - -

how can I make them signed , with details if possible !
my description


Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity add_sust is
port( E1 : in std_logic_vector(3 downto 0);
      E2 : in std_logic_vector(3 downto 0);
      a  : in std_logic_vector(1 downto 0);
      s1  : out std_logic_vector(7 downto 0));
end add_sust;
architecture aaddsust of add_sust is

begin
 process(a,E1,E2)
   
  begin
   if(a="01") then 
        s1<= "0000" & E1+E2;
      elsif(a="10") then 
        s1<="0000" & E1-E2;
      elsif(a="11") then 
        s1<=E1*E2;
   end if;
end process;
end aaddsust;
 

This makes them signed types:

Code: 
entity add_sust is
port( E1 : in signed(3 downto 0);
      E2 : in signed(3 downto 0);
      a  : in std_logic_vector(1 downto 0);
      s1  : signed(7 downto 0));
end add_sust;
architecture aaddsust of add_sust is

Also a note on your code - it creates latches. You do not assign a value to S1 when a = "00, and hence s1 will create latches, which are not that great in FPGAs.
 
Re: add and subtract and multiply 4 bits &quot;help&quot;

shall I add
Code: 
use ieee.std_logic_signed.all;
or replace the unsigned by signed ?

- - - Updated - - -

Untit5656led-2.png
how cann I fix that ?
 

you should remove std_logic_signed if you want to be VHDL standards compliant - it is a non-standard library. It treats std_logic_vectors as signed numbers, when you should really be using the signed type.

The problem you see is that you pre-loaded the E1 signal with "0000", making it a +ve number. You need to sign extend it. With the numeric_std library, you can do it like this:

s1 <= resize(E1, 8) + E2;
 
TrickyDicky said:
you should remove std_logic_signed if you want to be VHDL standards compliant - it is a non-standard library. It treats std_logic_vectors as signed numbers, when you should really be using the signed type.
Click to expand...

While I almost never agree with TD on this subject, this is one of the times I do. Comparisons and multiplication are different for unsigned vs signed, so there is value in using signed vs unsigned.

If you are unhappy with the types, you can always use casting, extra signals, variables, etc... You can cast to signed/unsigned, then cast back later if needed for std_logic compatibility.
 
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