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[SOLVED] power amplifier PAE query

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natnoraa

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Hi,

I am posting this thread which i've sought help in another forum.

I have a question. Given a simple bias circuit of a nmos, I would like to check the PAE it probably can go.

Am running Cadence Virtuoso Spectre and the result is that a simple class C PA gives me lower PAE than Class AB or even Class A? Does anyone know the reason for it?

I have already made sure the power at the 2nd, 3rd harmonics are well below -20dBm from the fundamental o/p power and from the PSS function, i checked on PAE and selected the fundamental frequency in which i would like to measure its PAE.

I have also used a simple LC oscillator tank to make sure i've filtered out all the harmonics leaving only the fundamental.

Vth is about 0.55V so I assume Vg below that would be Class C, such as 0.4V, 0.3V etc.

Any help would be appreciated. Thanks!

PAE.png
 

Did you check all waveforms (both current and voltage) for the class B and C designs? Drain efficiency depends on the termination (as seen by the active device) for harmonics.

Do you still have significant gain when operating at class C (as gain reduces when reducing conduction angle). At some conduction angle, you will notice a reduction in drain efficiency (hence PAE) because of Rdson limitations. Reducing the conduction angle means larger peak current, hence more Rdson loss.
 
Hi WimRFP,

Thanks for your interest in this thread and your reply.

I have found out that the PDK's nfet model that I am using has a sharp gain roll-off after 30-40GHz. At Class C operating regime, the Pout is significantly reduced due to the very low gain (sometimes even -ve which resulted in -ve PAE). From the formula of finding PAE, I can see why the PAE is this low for a Class C at the operating frequency of my interest. Thanks again for the helpful tips! the current waveform using PSS current plot vs time doesn't look good.

Natnoraa
 

Output and Input impedances which are seen by transistor extremenly important to get the right PAE and Pdel. First, you should do Load Pull Simulation to obtain PAE and Output Power Contours and their max. values where these impedances are optimum for those requirements.Otherwise PAE and Output Power will be less than desired. PAE(max) point is generally a distance from Pdel(max) point therefore your make a decision between these two compromising points.Then you have to match output and input to regarding these optimum impedances.

and before all these, you must fix. the bias for a proper c-class operation by observing Drain current while input and output have initially been terminated by 50 Ohm.
Then,apply Load Pull and then observe the current again, if it's necessary shift the bias..then optimize your circuit .
 
Hi BigBoss,

Thanks for your reply! Indeed I have not done o/p or i/p matching to the circuit for the results shown. I understand that a load pull is necessary for large signal especially for a rf pa. However I have the constraint of working with the foundry's model only in cadence virtuoso. Hence running a load pull simulation can only be done for output power contours but cannot simulate a load pull for PAE or other parameters. (sorry but may i ask in this instance your Pdel refers to?)

Thanks for your advice! I'll look into this again. However, I have tried to sweep Vgs from 0V to 0.5V with a step of 0.05V (Vth is about 0.55V) and none of them can actually give me anywhere near the 'theoretical' value. not even 30% for a class C pae whereas for a class ab or class a it can hit about 20%+. As i have mentioned earlier, the gain roll off is too much at my operating frequency. PAE = [(G-1)*Pin]/Pdc

I have even done load pull for a class C but max it can give is only about 20% odd for a single transistor. I have to probably do another architecture.

P.S: I have actually picked up new knowledge every now and then from reading your replies to others. A big thank you

natnoraa
 

natnoraa said:
Hi BigBoss,

Thanks for your reply! Indeed I have not done o/p or i/p matching to the circuit for the results shown. I understand that a load pull is necessary for large signal especially for a rf pa. However I have the constraint of working with the foundry's model only in cadence virtuoso. Hence running a load pull simulation can only be done for output power contours but cannot simulate a load pull for PAE or other parameters. (sorry but may i ask in this instance your Pdel refers to?)

Thanks for your advice! I'll look into this again. However, I have tried to sweep Vgs from 0V to 0.5V with a step of 0.05V (Vth is about 0.55V) and none of them can actually give me anywhere near the 'theoretical' value. not even 30% for a class C pae whereas for a class ab or class a it can hit about 20%+. As i have mentioned earlier, the gain roll off is too much at my operating frequency. PAE = [(G-1)*Pin]/Pdc

I have even done load pull for a class C but max it can give is only about 20% odd for a single transistor. I have to probably do another architecture.

P.S: I have actually picked up new knowledge every now and then from reading your replies to others. A big thank you

natnoraa
Click to expand...

There is a Variable Tuner component in one of the Cadence libraries to my knowledge.You can also use this variable tuner to plot Delivered to Load Power ( Pdel) and PAE with some scripts/formulaes.It shouldn't be very hard to implement.Input matching essentially doesn't change too much output power maybe some minor effects.For a c-class amplifier PAE is also function of Available Power from source.It's important..!!
By choosing a right OP for that amplifier, C-class can reach to much higher PAE values.
If you are able to use ADS ( Golden Gate of Agilent ) in Cadence ADE, use the Design Guide for PAs in ADS.There are many Design Guide templates that are extremely useful.
I have recently designed a C-class amplifier @2.4GHz by using ATF-50189 ( Avago )and PAE can reach %72 @ 24dBm Pdel.
 

Regarding the gain roll-off: Did you use the actual input power to the nfet (in a linear system: Pfwd-Prefl), or Pfwd? Are you able to "measure" current and voltage inside the nfet model? The reason for this is to measure the actual drift current (drain current minus displacement/capacitive current) and voltage across the active region. This enables you to see what is happening at/inside the chip.
 

Hi,

Thanks for the reply bigboss. I understood that it's the portadapter that's being used for the simulation.

WimRFP: I'm not able to use the actual input power but in fact, swept the input power from -20dBm to about 15dBm. The simulations do not allow me to measure the current and voltage inside the nfet model from the PDK sadly. It's still at a stage of simulation using cadence spectre.

Natnoraa
 

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