Milruwan
Member level 1
I implement a Zero crossing detector in a fpga. It can detect the zero crossings of a signal and it could successfully demodulate a FM modulated signal. The problem is the demodulated signal doesn't have a fixed sample rate,Because when a zero crossing is met counter will start. when the other zero crossing is met counter save the present value to a register and restart the counter.This process will continue.... The value of the register is the demodulated signal.But it doesn't have a fixed sample rate. So the demodulated signal cannot be filtered.
1) How to get a fixed sample rate?
2)What is the sample rate we should take as the sampling rate of the filter?
3)How to overcome this problem?
1) How to get a fixed sample rate?
2)What is the sample rate we should take as the sampling rate of the filter?
3)How to overcome this problem?