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serdes vs transceiver

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soloktanjung

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Hi,

I need some clarification regarding serdes and transceiver. I know what serdes is and i just read xilinx user guide on transceiver (7series transceiver user guide) and did not understand clearly.

Is serdes functionality is a part of the MGT (multigigabit transceiver) or is it a different component?

thanks.
 

The GT* tiles are more advanced version of serdes. FPGA's run at around 100-400 MHz in practical designs, but IO's are now much faster. The SDR registers would limit IO to 400Mbps/IO. DDR would only be around 800Mbps/IO. But SERDES allows for 1600Mbps/IO (or a bit higher). Still 1.6Gbps isn't close to "high performance". That's where the GTP/GTX/GTH/GTZ come in. These specialized IO can run in the 1.25-27Gbps range. Next gen FPGAs will even have 50+ Gbps IO. 10Gbps would be a 32b bus @ 312.5 MHz.

In short, the SERDES are different (lower performance) than the MGTs (higher performance).
 
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