sharath666
Advanced Member level 2
Hi. Could anyone tell me why is setup checked for a latch at the negedge even though for all the flops in the same design, it is checked at posedge?
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I also wanted to know whether a clock gating circuit which uses posedge triggered latch(which is transparent when the clock is high) will work. .
What I said before applies when the setup check is performed on a standalone negedge latch(if the time borrowing is allowed, setup check can be done on pos edge). A clock gating cell with a neg edge latch in it has a little different character and the setup check must be done on pos edge.Then I found out that setup checks on a latch are done on a negedge and not on posedge. So I wanted to know why are setup checks done on the negedge in a latch
A clock to a latch and an AND gate in a clock gating cell must be on opposite polarity to avoid a glitch. If you use a pos edge latch, the clock to the AND gate must be inverted, which makes the clock gating cell provide the inverted clock. It works if you want to invert the clock at the clock gating cell.and I also wanted to know whether a clock gating circuit which uses posedge triggered latch(which is transparent when the clock is high) will work. My first question is already answered and my second q
uestion is what I have asked now.