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[SOLVED] Neg Edge used for latch

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sharath666

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Hi. Could anyone tell me why is setup checked for a latch at the negedge even though for all the flops in the same design, it is checked at posedge?
 

a neg edge latch becomes transparent when the clock is low and you generally want the input data to settle before the latch becomes transparent(unless you allow the time borrowing). This makes the setup analysis to be done on falling edge of the clock.
A flop has the same neg edge latch as a master latch, but the path to a slave latch is closed when clock is low, so that even though the input data changes when clock is low, the data doens't propagate to the output pin of the flop. It means that the input data needs to settle before the path from the master to slave latch open up, which is when the clock goes high. So, the setup check is performed on rising edge.
 
So will a clock gating circuit having a rising edge clock going to the latch not serve the functionality (I mean a circuit having no bubble on the clock input of the latch)?
 

The motivation for me to ask my first question was the curiosity I had when I saw a clock gating circuit which had a latch with a bubble on the clock pin(so it uses negedge instead of posedge). Then I found out that setup checks on a latch are done on a negedge and not on posedge. So I wanted to know why are setup checks done on the negedge in a latch and I also wanted to know whether a clock gating circuit which uses posedge triggered latch(which is transparent when the clock is high) will work. My first question is already answered and my second question is what I have asked now.
 

I also wanted to know whether a clock gating circuit which uses posedge triggered latch(which is transparent when the clock is high) will work. .

The posedge triggered latch for clock gating circuit will clip the clock pulse if clock is gated when clock pulse is high. That is why negedge triggered latch is used so that even though gating signal changes during high period of clock it is not passed until clock low period.

In short, the posedge triggered latch will not work.
 

Then I found out that setup checks on a latch are done on a negedge and not on posedge. So I wanted to know why are setup checks done on the negedge in a latch
What I said before applies when the setup check is performed on a standalone negedge latch(if the time borrowing is allowed, setup check can be done on pos edge). A clock gating cell with a neg edge latch in it has a little different character and the setup check must be done on pos edge.
A clock gating cell consists of a neg edge latch and an AND gate whose inputs are a clock(non inverted) and the output from the latch. When the clock is low, the latch is transparent, but the output of the latch is blocked by the AND gate as the clock, another input to the AND gate, is 0. This tells that even though you have the input(enable) signal to the clock gating cell changes when the latch is transparent, the output of the clock gate cell doesn't get a glitch. So, the input date to the clock gate has a full cycle to settle, not a half cycle, so that you should do the setup check on posedge. If your cell library provides a neg edge as an associated clock edge for setup check, the library is not correctly made.

and I also wanted to know whether a clock gating circuit which uses posedge triggered latch(which is transparent when the clock is high) will work. My first question is already answered and my second q
uestion is what I have asked now.
A clock to a latch and an AND gate in a clock gating cell must be on opposite polarity to avoid a glitch. If you use a pos edge latch, the clock to the AND gate must be inverted, which makes the clock gating cell provide the inverted clock. It works if you want to invert the clock at the clock gating cell.
 

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