me0414013
Junior Member level 3
While simulating my vhdl code in modelsim.
I am getting some warning like
-----------------------------------
# ** Warning: NUMERIC_STD."/=": metavalue detected, returning TRUE
# Time: 0 ps Iteration: 0 Instance: /---/--/--/--
-------------------------------------
And I am getting the output as expected.
I came to know that the warnings are because of uninitialized variables..
but doubted will there be any problem when it goes on to the real fpga implementation..
I made sure that the code is synthesizable(in ISE) ...
will there be any problems because of the uninitialized variables when in it goes into the board????
thanks in advance..
I am getting some warning like
-----------------------------------
# ** Warning: NUMERIC_STD."/=": metavalue detected, returning TRUE
# Time: 0 ps Iteration: 0 Instance: /---/--/--/--
-------------------------------------
And I am getting the output as expected.
I came to know that the warnings are because of uninitialized variables..
but doubted will there be any problem when it goes on to the real fpga implementation..
I made sure that the code is synthesizable(in ISE) ...
will there be any problems because of the uninitialized variables when in it goes into the board????
thanks in advance..