Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Regarding simulation warnings in modelsim and uninitialized variables

Status
Not open for further replies.

me0414013

Junior Member level 3
Joined
Aug 30, 2012
Messages
28
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
ongole
Activity points
1,504
While simulating my vhdl code in modelsim.
I am getting some warning like
-----------------------------------
# ** Warning: NUMERIC_STD."/=": metavalue detected, returning TRUE
# Time: 0 ps Iteration: 0 Instance: /---/--/--/--
-------------------------------------

And I am getting the output as expected.
I came to know that the warnings are because of uninitialized variables..
but doubted will there be any problem when it goes on to the real fpga implementation..
I made sure that the code is synthesizable(in ISE) ...
will there be any problems because of the uninitialized variables when in it goes into the board????
thanks in advance..
 

On the real board, values can only be '0' or '1'. So as long as you dont care what the power up state is, then there will not be a problem. You can supress those warnings in modelsim under "simulate"-> "runtime options" -> "supress messages from IEEE packages"
 
power up state means the initial state when your system power up or starts.

Usually it is a good habbit to use the reset system as soon as system power up to take it back to some predefined state, for example either relevant registers become all ZEROS or something else of your choice.

Hope this helps
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top