worst case timing of a sub-module using synopsys design compiler

Hi friends,

I want to know how can i find out worst case timing of a sub-module of a Verilog design using Synopsys design compiler.

Please let me know if you have any questions.

If i understand your question correctly, you wish to identify the worst timing path within a module in the design. Something like paths within an IP.

There are three ways i can quickly think of - (i like the first one more easier to implement)

a. identify the clocks going to this module and create a generated clock(same freq) just a level above this module. Now using this you can report paths for this clock. Repeat if there are more clocks. This works only if you can identify unique entry point to this module for the main clock else you may end up seeing more paths / endpoints as well.

b. Using TCL. Try making a list of all registers, Inputs and outputs in that module a quick find or a get_* (depending on what your using RC or DC) will help you get that. In a loop start reporting timing to and from these paths with slack limit 0 - this will filter the unconstrained and positive paths. This is similar to using report timing with a register or inp / op within that module

c. Use "current_design" in DC or derive_environment in RC, not sure if these will be accurate timing numbers cause i believe they do some kind of extraction of timing but atleast here you should get the active start and endpoints.

Hope this helps...