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How to avoid unwanted logic removal during synthesis?

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KHDAK

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Hi All,

I am synthesizing a processor design with Cadence RTL compiler. The synthesized netlist works fine (in simulation) and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized the same files with a tighter clock constraint (1800- 3000ps) the RTL compiler meets the timing constraint but randomly removes some of the registers(i.e Register file of the processor) in the synthesized netlist, which are required for proper operation of the design and are not some undriven or extra logic. Is there a way to instruct RTL compiler what not to remove?

The attributes I am using are as follows:

set_attribute hdl_track_filename_row_col true /

set_attribute hdl_undriven_signal_value 0

set_attribute hdl_infer_unresolved_from_logic_abstract false /

set_attribute information_level 2



Thanks.
 

Re: How to avoid unwanted logic removal during synthesis

I'm more of an FPGA guy, but some optimizations -- retiming in particular -- modify the design in logically safe ways in order to meet timing. The nets may still be in the design under a different name.

Secondly, are you certain you are building/testing the correct files? "randomly removing used logic" often occurs when there are accidental duplicates of modules/files/netlists where the simulation is done with a different set than the synthesis/implementation.
 

Re: How to avoid unwanted logic removal during synthesis

permute said:
I'm more of an FPGA guy, but some optimizations -- retiming in particular -- modify the design in logically safe ways in order to meet timing. The nets may still be in the design under a different name.

Secondly, are you certain you are building/testing the correct files? "randomly removing used logic" often occurs when there are accidental duplicates of modules/files/netlists where the simulation is done with a different set than the synthesis/implementation.
Click to expand...

Thanks for the reply permute! Yes I am sure I am using the right files as the Netlist with looser timing constraint is also built from the same files. Is there a command in RTL compiler for "Retaining Hierarchy" as there is in Xilinx ISE ?
 

Re: How to avoid unwanted logic removal during synthesis

I would check the logfile to identify the reason for which the register is removed. TRy setting the information level to 9 and search that register. RC will tell you a reason why the registers where optimized.

Retaining hierachies you mean avoid ungrouping. I would say yes, set the attr auto_ungroup to none.
 
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    KHDAK

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Re: How to avoid unwanted logic removal during synthesis

KHDAK said:
Hi All,

I am synthesizing a processor design with Cadence RTL compiler. The synthesized netlist works fine (in simulation) and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized the same files with a tighter clock constraint (1800- 3000ps) the RTL compiler meets the timing constraint but randomly removes some of the registers(i.e Register file of the processor) in the synthesized netlist, which are required for proper operation of the design and are not some undriven or extra logic. Is there a way to instruct RTL compiler what not to remove?

The attributes I am using are as follows:

set_attribute hdl_track_filename_row_col true /

set_attribute hdl_undriven_signal_value 0

set_attribute hdl_infer_unresolved_from_logic_abstract false /

set_attribute information_level 2



Thanks.
Click to expand...

I think you should carefully define the clock constraint, its the only single way to tell design compiler something u want to tell.
 

Re: How to avoid unwanted logic removal during synthesis

englishdogg said:
I would check the logfile to identify the reason for which the register is removed. TRy setting the information level to 9 and search that register. RC will tell you a reason why the registers where optimized.

Retaining hierachies you mean avoid ungrouping. I would say yes, set the attr auto_ungroup to none.
Click to expand...

Thanks englishdogg! As it turns out synthesizer had renamed/grouped some of the registers hence it is not possible to locate them in Netlist. So I am now saving the results to external memory where I can easily check them.
 

Re: How to avoid unwanted logic removal during synthesis

To my knowledge of RTL Compiler, it would not rename the register entirely just add a suffix "_reg" and the bit number in "[1]" or something like that, which is also controllable using some attributes. But glad that you could proceed
 

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