rfub
Newbie level 6
Hi all,
I want to build an I2C interface between Aptina CMOS sensor and Xilinx FPGA board to do some image processing. I only have some basic FPGA experience(such as calculator or electronic locker developed in Xilinx ISE in Verilog) and I've never done image processing before.
After reading the Aptina MT9J003 CMOS sensors datasheet, I still don't quite understand how to start with it. There are bunch of input and output signals and thousands of registers in the Aptina sensor, as each pixel are described in 12 bits parallelism during the pixel clock period, how can I enter into pixel? The VHDL or Verilog code should have several functionalities such as Bad pixel correction, FPN correction, vignetting compensation, gamma correction, histogram equalization, etc. The output of FPGA should be a .bit file contains the pixel information.
Does anyone have experience in FPGA image processing or is there any existing IP Core or HDL code available on line? I have contributed a lot of time in reading the documentation but still couldn't fine a way. I really need help, any information could be appreciate. Thanks a lot!!
I want to build an I2C interface between Aptina CMOS sensor and Xilinx FPGA board to do some image processing. I only have some basic FPGA experience(such as calculator or electronic locker developed in Xilinx ISE in Verilog) and I've never done image processing before.
After reading the Aptina MT9J003 CMOS sensors datasheet, I still don't quite understand how to start with it. There are bunch of input and output signals and thousands of registers in the Aptina sensor, as each pixel are described in 12 bits parallelism during the pixel clock period, how can I enter into pixel? The VHDL or Verilog code should have several functionalities such as Bad pixel correction, FPN correction, vignetting compensation, gamma correction, histogram equalization, etc. The output of FPGA should be a .bit file contains the pixel information.
Does anyone have experience in FPGA image processing or is there any existing IP Core or HDL code available on line? I have contributed a lot of time in reading the documentation but still couldn't fine a way. I really need help, any information could be appreciate. Thanks a lot!!