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Size of FPGA Mulipliers

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shaiko

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Microcontoller / DSP internal multipliers are generally of x8 bit size - with 32 x 32 being very common.
Why are emmbedded FPGA multipliers of very different size? (25 x 18 , 18 x 18 , etc...)
 

They often have in built accumulators after the mult, so it allows extra accumulation.
 

but in order to do full 32x32 bit multiplication - a 28x28 bit won't be enough dictating the use of 2 such multipliers and slowing the overall algorithm. So what is the point ? Why use such "unorthodox" sizes ?
 

it doesnt slow it at all, you can use 2 mults in parrallel (but on most families, it quotes mults in terms of 18x18 or 36x36 - four 18x18 mults make a 36x36)
 
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    shaiko

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The Odd size is basically because these multiplier are part of DSP slices...and they are configurable...we can cascade 2 or 3 multiplier.. They are designed in a way that they can be configured as other logic devices too....where as multipliers in DSPs or in microntrollers are dedicated...they just do multplication...and there width is decided by ACC width basically microcontroller width.
Hope it is helpfull to you..
 
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