Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

ddr3 length matching

Status
Not open for further replies.
P

patilpradeep

Junior Member level 1
Joined
Apr 4, 2013
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,364
My design consists of 5 DDR3 (64 bit + 8 bit ecc) . placed ddr in board is TOP & bottom format and i want to use flyby topology for routing. how to match the length in address group.???? what is the length tolerance???
 

sivamani said:
use tight tolerance around +/- 10 mils
Click to expand...

1st memory is on topside & 2nd on bottom... for address minimum length is 60 mil & longest is 300 mils between 1st ddr to 2nd ddr ....because of top & bottom placement i cant maintain +/- 10mils .... is there anyother suggestions ? is that necessary match the length??
routing.jpg

snapshot is for your reference.. by this you can understand my query..
 
Last edited:

make sure that the stub length should be very minimum and match lengths chip wise . like maintain equal length from Controller to 1 st ddr3 as a group and 2nd set controller to 2nd DDR3 etc..

Do u have signal integrity tool?If yes then we can simulate how the stub is effecting signal from quality point of view..

And also please go thru write leveling and read leveling concept for better understanding on length matching...

refer
https://www.edaboard.com/threads/255905/

for some more details...

go thru the attached document it will really help you..
 

Attachments

  • tn4113_ddr3_point_to_point_design.pdf
    620.2 KB · Views: 104
Last edited:
Hello sivmani,

I ve on more doubt regarding X'talk report generated in batch simulation in allegro SI tool,
Xtalk.jpg


in this some nets showing odd & even Xtalk, what is tolerance(limits) for this Xtalk values????
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top