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scan testing description

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sun_ray

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Can anybody please let me know about scan testing and hot it happens.
 

Scan Testing is the basic of DFT.
In which we convert the normal flops to scan flops by adding extra features in the flop to make the flop to flop path testable, To increase the controllability and observability of each and every node.

You just refer the attached docs :
 

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Is it that the only purpose of putting a scan chain is that to help the ATPG tool to generate proper test vectors such that the ATPG tool can place different test vectors and chose which test vector will be proper for the design?
 

The main purpose is to make design testable with the help of incresing the controllability and observability of each and every node of the design.
Thn if the pattern fails thn post silicon debug is more simpler for finding the physical defects.
 

Is it that there will be separate scan chains for each register to register path with each scan chain having its own separate scan input?
 

maulin sheth said:
Please look at the above attached..it will give you the answer of your questions....
Click to expand...

I looked at. But they do not answer my query clearly. Can you please answer to my last query?
 

sun_ray said:
Is it that there will be separate scan chains for each register to register path with each scan chain having its own separate scan input?
Click to expand...

As you mentioned, Can you give me the answer of what do you mean by separate scan chain for each register to register path? and also that what do you mean by the scan chain having own separate scan input?
 

maulin sheth said:
As you mentioned, Can you give me the answer of what do you mean by separate scan chain for each register to register path? and also that what do you mean by the scan chain having own separate scan input?
Click to expand...

There will be a combinational cloud between two register banks. So the design in this way will have many different register banks and with combination logics inserted between them. My question was that is it for each register bank there will be a separate scan chain?

Regards
 

sun_ray said:
There will be a combinational cloud between two register banks. So the design in this way will have many different register banks and with combination logics inserted between them. My question was that is it for each register bank there will be a separate scan chain?

Regards
Click to expand...

Yea...But I want to know that you have use word like Separate Scan chain..what do you mean by separate scan chain?
If possible thn post a image of whatever you understood...
 

maulin sheth said:
Yea...But I want to know that you have use word like Separate Scan chain..what do you mean by separate scan chain?
If possible thn post a image of whatever you understood...
Click to expand...

Separae scan chain mean scan chain for each register bank.
 

It is not necessary that the different register bank contain different scan chains...
May be single register bank contain more than 2 scan chains.....or may be two register bank contain only 1 scan chain...
so it is not requirement of the scan testing...But every scan chain have a different input pin...
 

thanks for all the information guys

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thanks for all the information guys

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thanks for all the information guys

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thanks for all the information guys

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