Basic doubts about MOSFETS

Hi,

I have a few general questions about MOSFETs.
1. How exactly do we define the resistance of a MOSFET ? Vds/Ids ?

2. How does the resistance of a MOSFET vary across the three regions(subthreshold,Linear and Sat) of operations ? Also in many places i found that we talk about the transconductance of the MOS when it is in saturation region.
i believe Subthreshold would be very high resistance. Linear would be an increasing resistance where as Saturation would be again infinite ( looking at the Id vs Vds characteristics of mOS). Is this correct?

3. Why do we use the MOS in saturation region when we need it to behave as a Switch (as the resistance for it will be pretty high)? Is it because of the constant current that we can obtain through it?

1. Ideally, MOSFET have 0 resistance when on i.e. saturation and infinite resistance when off. In practice, it has nigligible on resistance and very high off resistance. Using ohm's law is one way to find out the resistance. but generally linear region resistance is also very small. Look into the datasheet to find all these parameters.
2. MOSFET is a voltage controlled current source i.e. transconductance device, a small variation in input voltage make large change in current through MOSFET. Voltage control is done by gate voltage. More is the gate voltage, more is the induced charges between source and drain, so more is the conductance, so resistance decreases. So, when MOSFET is fully on, the resistance is negligible, the conductance is highest. The threshold is the minimum gate voltage required to make MOSFET start conducting and decrease the resistance. So, drain to source resistance is inversely proportional to gate voltage, its gate voltage function. Since, the resistance becomes very low when threshold is crossed, hence, the amount of conductance increases, so we talk about conductance of drain to source or transconductance from gate.
3. MOSFET's are used mostly as switch, so when mosfet is on, there is almost 0 resistance across it and high current flows, since the resistance is almost 0, the amount of voltage drops is less too. Again in OFF state, there is no current flows across mosfet, but full voltage appears across drain to source. So in both on and off state, the overall power usage is very low, while in linear region, both voltage and current exists due to limited resistance of mosfet hence, power dissipation occurs.

hope that helps.

The gate resistance is very high but reduces as you reduce your technology , below 90nm you need to really consider gate currents.
the the drain source resistance is called rds, in saturation rds = Va/Drain current, Va = early voltage, so I is the main knob we use, though changing the length of the device does change its early voltage.
also if you are measuring the output impedance then you need to take into account the vccs, vgs*gm. iin some configurations this can be low and ignored in other configurations you must account for it.
subthreshold region has same rds equation.
In linear region rds =1/(k'*W/L*(vgs-vt))
to give you an idea of resistance value, in my current process of .18 typical rds value i work with are around 100k. a 1/gm resistance is around 2k.
The above post was referring solely to large signal. what I am referring to is small signal.(dc vs ac). Rds is typically lower in saturation than subthreshold. simply due to subthreshold operating with lower currents. as far as switches, operating in saturation...are you sure this is the case? if you apply a 1.8V signal on a gate of a nfet, and pass a 1V signal from the drain to the source, the vds becomes tiny because you are passing a voltage, so vds might be near 0. 0 <(1.8-.4), using .4 as Vt. so the switch would be in linear region.

-Pb

@prestonee : For the MOS as switch i too had the same doubt that with the device being in linear we can attain Vds = 0, rather than for device in saturation which would have a Vth drop. Also I recently read in a doc that mentioned that the MOS is used in cut-off and linear region when used as a switch and for amplifier it is in saturation.
I have one more doubt wrt resistance. Res (sat) < Res (Subth) as u mentioned above because of the current. But how about the relation wrt Res (Linear) ? And also for the saturation region if my current that i am working with is very small (nA) then again my resistance would shoot up right ?

it can obtain 0 vds if the other end of the switch is open , or going to a gate. since linear the vgs-vt term isnt squared you should be able to have smaller resistances(squaring a fraction makes a smaller number and so 1/small number = big number in case of saturation, so linear will have smaller resistance in same conditions. just work with the math.
-Pb

I am actually trying to design a bandgap reference and the currents in that case are in nA. The circuit uses subthreshold MOS but needs current mirrors to mirror the current in branches. For that case i would need to have the PMOS and NMOS in saturation right ? I did achieve that with some size values but my concern is that in actual fabrication the sizes may vary and that can cause the whole thing to fail.
Also one of my doubt is since i am anyways dealing with nA of current why cant i use subthreshold mode for the mirror devices, as the res for them would also be huge? Would the exponential current be the problem as small shift in device sizes => change in Vds or Vth, Vgs => large change in current ? Or there is some other reason ?

For starters I am not aware of very many successful low current bandgaps. the reason is modeling and characterization more then anything as afar as I know.
In my company we have to worry about yield as well as performance. To maximize yield we verify devices are operating within tsmc WAT data specifications for predictability.
The reason we use mirrors in strong saturation is for matching. The (1+lambda Vds-vt ) term in saturation causes less impact then the (1-e^(vds/vt)) of subthreshold region.

the exponential term in subthreshold for current is the vgs term not the w/l term, in both saturation and subthreshold w/l has linear impact. its primarily vds, as a vgs^2 is not too much off from an e^vgs as far as impact.

-Pb