samiksha
Junior Member level 1
hi
i m designing a bypassing multiplier. nd in this by checking the multipler bit, we can bypass a particular row or clumn so as to reduce switching activity. but in verilog, conditional use of generate statement is not being supported for bypassing. the reason is while elaborations, we cant conditionally call any other module. so what shud i do to conditionally instantiate or skip any instantiation in verilog?
i m designing a bypassing multiplier. nd in this by checking the multipler bit, we can bypass a particular row or clumn so as to reduce switching activity. but in verilog, conditional use of generate statement is not being supported for bypassing. the reason is while elaborations, we cant conditionally call any other module. so what shud i do to conditionally instantiate or skip any instantiation in verilog?
