madalin1990
Full Member level 2
I have a problem with this simple 3 to 1 mux:
I wrote a simple testbench:
It is working fine except when sel=10,because instead of directing in2 to out,it enters the undefined state.
Code:
module MUX3TO1(IN0,IN1,IN2,SEL,OUT);
input [23:0] IN0,IN1,IN2;
input [1:0] SEL;
output reg [23:0] OUT;
always @(SEL or IN0 or IN1 or IN2)
case( SEL )
00:OUT <= IN0;
01:OUT <= IN1;
10:OUT <= IN2;
default: OUT<=24'bx;
endcase
endmoduleI wrote a simple testbench:
Code:
module TB_MUX3_TO_1();
reg [23:0] IN0,IN1,IN2;
reg [1:0] SEL;
wire [23:0] OUT;
initial begin
$display ("time\t IN0 IN1 IN2 SEL OUT ") ;
$monitor ("%g\t %b %b %b %b %b ",
$time,IN0,IN1,IN2,SEL,OUT);
IN0 = 24'b000000000000000000000011; //3
IN1 = 24'b000000000000000000000101; //5
IN2 = 24'b000000000000000000000111; //7
SEL = 2'b00;
#5 IN2 = 24'b000000000000000000000101; //5
#2 SEL = 2'b01;
#5 IN0 = 24'b000000000000000000000100; //4
#4 IN1 = 24'b000000000000000000000110;//6
#2 SEL = 2'b10;
#4 IN1 = 24'b000000000000000000000111;//7
#10 SEL = 2'b00;
end
MUX3TO1 U_MUX3TO1 (
IN0,
IN1,
IN2,
SEL,
OUT);
endmoduleIt is working fine except when sel=10,because instead of directing in2 to out,it enters the undefined state.
