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how to display all the timing paths between input and output ports (design compiler)

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vikipsg

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Hi,

I am using Design compiler. I have to display all the paths between input and output ports of a design, including those that do not violate the timing constraint.

Can you all help me how to write the script to report this?

Thanks & Regards,
Vignesh
 

set in_ports [get_ports [list "list all your input ports here"]] ; ##or you can try set in_port [all_inputs]
set out_ports [get_ports [list "list all your output ports here"]]; ##or you can try set in_port [all_outputs]
set in_to_out_paths [get_timing_path -from $in_ports -to $out_ports -nmorst 1000000000 -max_paths 1000000000]
foreach_in_collection sig_path $in_to_out_paths {
set start_in_port [get_attribute $sig_path startpoint]
set end_out_port [get_attribute $sig_path endpoint]
set start_name [get_object_name $start_in_port]
set end_name [get_object_name $end_out_port]
puts "your_log_file_name" "$start_name -> $end_name"
}
 
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